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Senior Physical Design Engineer
San Jose, CAJob Title: Senior Physical Design Engineer
Location: San Jose, CA or Remote (work from any US location)
US work status: US Citizen or US Permanent Resident only
Responsibilities:
• Define PD requirements by working closely with the front-end team, understand the chip architecture and drive physical aspects early in the design cycle
• Physical design tasks such as synthesis, PnR, timing closure, area improvement, floorplanning, clocking, I/O planning and power optimization
• Discussions with 3rd party IP providers, foundry partners and design services
• End to end tasks from flow development to sign-off
• Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL, and evaluate synthesis, timing and power results
Requirements:
• BSEE with 7+ years of industry experience.
• Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools
• Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows
• Experience with back-end design tools such as PrimeTime, Innovus, RedHawk, etc.
• Knowledge of low-power design flows such as power gating, multi-Vt and voltage scaling
• Strong programming skills in Tcl/Perl/Shell/Python
• Excellent understanding of logic design fundamentals and gate/transistor level implementation
• Exposure to DFT is an asset
• Prior experience working on high performance technology nodes and understanding of deep sub-micron design problems/solutions
• Strong problem solving and debug skills across various levels of design hierarchies
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The anticipated annual base salary for this position is between $130,000 - $180,000 which also includes a comprehensive benefits package.
Equal Opportunity Policy Statement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
Our Management team is dedicated to this policy with respect to recruitment, hiring, placement, promotion, transfer, training, compensation, benefits, employee activities, and general treatment during employment.
Location: San Jose, CA or Remote (work from any US location)
US work status: US Citizen or US Permanent Resident only
Responsibilities:
• Define PD requirements by working closely with the front-end team, understand the chip architecture and drive physical aspects early in the design cycle
• Physical design tasks such as synthesis, PnR, timing closure, area improvement, floorplanning, clocking, I/O planning and power optimization
• Discussions with 3rd party IP providers, foundry partners and design services
• End to end tasks from flow development to sign-off
• Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL, and evaluate synthesis, timing and power results
Requirements:
• BSEE with 7+ years of industry experience.
• Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools
• Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows
• Experience with back-end design tools such as PrimeTime, Innovus, RedHawk, etc.
• Knowledge of low-power design flows such as power gating, multi-Vt and voltage scaling
• Strong programming skills in Tcl/Perl/Shell/Python
• Excellent understanding of logic design fundamentals and gate/transistor level implementation
• Exposure to DFT is an asset
• Prior experience working on high performance technology nodes and understanding of deep sub-micron design problems/solutions
• Strong problem solving and debug skills across various levels of design hierarchies
---
The anticipated annual base salary for this position is between $130,000 - $180,000 which also includes a comprehensive benefits package.
Equal Opportunity Policy Statement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
Our Management team is dedicated to this policy with respect to recruitment, hiring, placement, promotion, transfer, training, compensation, benefits, employee activities, and general treatment during employment.