Senior/Lead Place & Route (Full-Chip/Top-Level, Netlist-to-Tapeout expertise)

Location: San Jose, CA, United States
Date Posted: 10-12-2017
Position Title: Senior/Lead Place & Route (Full-Chip/Top-Level, Netlist-to-Tapeout expertise)

Status: Full-Time Employment (W2)
Work Location: Bay Area, CA
Full Benefits:

Role & Responsibilities:

As the Senior Place & Route / Structural Design Engineer, you will have the responsibility to provide technical leadership for challenging R&D projects using state-of-the-art technologies, and actively contribute to the development of the Encore Semi engineering community, and participate to the company technical strategy.

Working in collaboration with Encore Semi’s customers, you will be part of the Encore Semi project team performing design, layout, and integration of complex RFICs for wireless communication. The team is focusing on both IPs and chip-level, and working closely with designers to ensure area and performance constraints are met. In this role, you will also contribute to making sure the digital and analog parts are interconnected properly using specific layout techniques.  A successful candidate is creative and enjoys working independently, operate as a self-starter, and has strong layout experience using tool based P&R.

As the full-chip lead for structural design you will be charged with resolving difficult signal-integrity and interconnect challenges during the integration phase. Your expertise in physical integration (P&R) for complex ICs with digital standard cells, memories, and analog components will be crucial for successful completion of various projects. Additionally, you will have career development opportunities in both the technical domain and leadership domain.

Required Qualifications & Responsibilities:

• BSEE required, MSEE preferred with 12+ years of expertise in standard cell Place & Route, CTS, floorplanning, timing closure, and physical verification
• Experience with structural design at both full-chip level and block-level, including pad-ring, power grid, clock tree, signal integrity
• Strong expertise in STA and timing closure for both block-level and top-level design using OCV methodologies
• Good working knowledge of Cadence Innovus and/or Synopsys ICC2 physical design tools
• Expertise in physical verification of digital and analog layouts using DRC and LVS and Antenna
• Able to perform parasitic extractions of the layouts and run Static Timing Analysis (STA)
• Experience in signal integrity and power integrity including analysis of power supply decoupling requirements and package interconnect
• Run all the checks as needed to release a chip to manufacturing
• Experience must include successful tape-out of multiple designs
• Proficient in scripting using Perl & TCL
• Strong communication and inter-personal skills, developing/driving concepts and ideas with other team members

Preferred Qualifications:

• Proficient in custom IC layout using Cadence Virtuoso for layout edits
• Experience working on digital layout in an environment where large parts of the chip is comprised of analog and RF components
• Experience with tools and CAD environment for mixed-signal designs

Company Profile:

Encore Semi is a successful Engineering Solutions company headquartered in San Diego, California. We build Centers of Expertise (San Diego, Bay Area, Austin, Raleigh, Longmont, New York, Boston) to support the semiconductor and electronics system industry in North America. Our teams of experts enable leading-edge projects in the areas of SoC design and embedded software life-cycle. We provide high-value through acceleration, performance improvement, optimization, and risk mitigation. Working at Encore Semi means a continuous exposure to the most advanced technologies and tools, collaborating with industry-leading teams which are our customers and long-term partners, and making the difference in challenging but exciting projects.

Encore Semi Career Path:
Sri Ram
Talent Acquisition
Encore Semi, Inc.
Saratoga CA

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