Senior RTL Full-Chip Integration Engineer

Location: San Jose, CA, United States
Date Posted: 05-24-2018
Position Title: Senior RTL Full-Chip Integration Engineer
Location: San Jose, CA
Status: Full-time

About the Team:
The growing Encore Semi Front-End Development team collaborates with customers to implement microarchitecture specifications in RTL and integrate internal and 3rd party IPs into SOCs to satisfy specific targeted functionality and performance goals.  You will build on a background of SOC RTL development for designs including processor / controllers, interconnects and peripherals to implement full-chip / top-level protocols connecting IPs together to deliver product solutions.

About the Project:
As a senior member of an SOC development team, you will be responsible for driving RTL Integration for the Full Chip SOC model which would include the RTL / Logic Design of the interfaces between the defined units, integrating the full-chip RTL with the Verification environments from the Integration Verification team and building the full-chip SOC simulation models.  One area of focus will be to design and implement various full-chip protocols (such as clocking and reset schemes and structures to enable DFT) which are required for full SOC functionality.  If you have experience with Integration RTL Design and Full-Chip SOC models, joining the Encore Semi Front-End Development team would be for you.

Minimum Qualifications:
• Hands on experience with FC RTL integration tasks on medium to high complexity SOC / ASIC designs
• Experience with logic design to deal with Full-Chip Integration challenges such as the implementation of clocking and reset protocols, power domains and DFT structure design is important.
• Experience with bringing up RTL Simulation models at the full chip level 
• Debug experience using debug tools like Verdi as well as lower level waveforms and debugging through RTL code
• Working knowledge of Verilog based RTL and System Verilog based test benches, BFM’s, Trackers, Checkers, UVM entities used for SOC design verification
• 7+ years of Design experience including working with Verification

Preferred Qualifications:
• Experience with SOC design verification at the Full Chip or IP Level
• Languages: Verilog, System Verilog, UVM/OVM, Specman
• Scripting languages/tools: PERL, TCL, Make
• Tools: Unix, Synopsys VCS, Verdi
• Architectures: CPU cores / microcontrollers, Memory Subsystems, On-die Interface routing / networks (such as cross-bars or other routers)

Education Requirements:
• Required: Bachelor's, Electrical Engineering
• Preferred: Master's, Electrical Engineering


About Encore Semi:
Encore Semi is a successful Engineering Solutions company. We build Centers of Expertise to support our many customers from the semiconductor and electronics system industry in North America. Our teams of experts contribute to leading-edge projects in the areas of SoC design and embedded software. We provide high-value through acceleration, performance improvement, optimization, and risk mitigation.  Encore Semi provides its engineering team members with continuous exposure to top advanced technologies & tools, participation in challenging yet exciting projects, and direct collaboration with its industry-leading teams, customers, and long-term partners. Learn more about the company’s great benefits and career path on our website.
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