Digital Physical Design Engineer

Location: San Diego, CA, United States
Date Posted: 07-03-2018
Position title: Digital Physical Design Engineer
Location: San Diego, CA
Status: full-time
About the team:
The growing Encore Semi SoC implementation team collaborates with our customers on design of advanced systems for wireless communication, networking, storage, and automotive using innovative new core architectures. Joining our team, you will build on a background of working with state-of-the-art semiconductor design.   
About the project:
Our Digital Physical Design Team is responsible for the execution complete netlist-to-GDSII flow for embedded digital circuits in Analog IP. The scope ranges from block-level design to chip-level for devices such as modems, transceivers, power management, and RF front-end. You will be part of a team responsible for the complete Physical Design Flow for embedded digital circuits. Tasks includes timing closure, including development of timing constraints required for implementation and signoff. Work on block level and chip-level signoff, including timing, physical verification, powergrid verification, logical equivalence, and power domain integrity. You are expected to develop new scripts and flows to improve implementation processes. You will be responsible for complete netlist-to-GDSII implementation of embedded digital circuits. Implement and develop low-power implementation methods, including use of headswitches, clock gating, multi-vdd, and multi-vth Block- and chip-level floorplanning, powergrid, placement, CTS, P&R, PV, timing, and Signal Integrity Analysis. You will work closely with analog design teams to implement highly-customized P&R solutions. 

Minimum Qualifications
Bachelor's degree and 5+ years experience in the following areas:
- Physical implementation (Floorplanning, CTS, STA) in advanced technologies
- Knowledge of STA tool and closure methodologies, including experience with Primetime
- Power grid, clock tree, and low-power reduction implementation methods
- Signal integrity and timing closure methodologies such as OCV/AOCV/Statistical
- Physical Verification, Conformal Low Power (CLP), IR drop analysis, Formal Verification
- Programming and scripting skills (Tcl, perl and/or C)

Preferred Qualifications
- Master's degree
- Power-aware yield estimation Vmin optimization of Semi-custom of structured blocks
- Clock tree analysis and optimization
- Strong verbal and written communication skills
Education Requirements
- Required: Bachelor's, Computer Engineering and/or Computer Science and/or Electrical Engineering
- Preferred: Master's, Computer Engineering and/or Computer Science and/or Electrical Engineering
About Encore Semi:
Encore Semi is a successful Engineering Solutions company. We build Centers of Expertise to support our many customers from the semiconductor and electronics system industry in North America. Our teams of experts contribute to leading-edge projects in the areas of SoC design and embedded software. We provide high-value through acceleration, performance improvement, optimization, and risk mitigation.
Encore Semi provides its engineering team members with continuous exposure to top advanced technologies & tools, participation in challenging yet exciting projects, and direct collaboration with its industry-leading teams, customers, and long-term partners. Read about the company’s great benefits and career path in our website.
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