High-Speed CPU Core Physical Design Engineers

Location: San Diego, CA, United States
Date Posted: 07-23-2018
Position title: High-Speed CPU Core Physical Design Engineers
Location: San Diego, CA
Status: full-time
 
About the team:
The growing Encore Semi SoC implementation team collaborates with our customers on design of advanced systems for wireless communication, networking, storage, and automotive using innovative new core architectures. Joining our team, you will build on a background of working with state-of-the-art semiconductor design.   
 
About the project:
As a high-speed physical design engineer you will be part of a team that will develop, implement, and verify high-speed processor cores using state-of-the-art tools and technologies. Tasks involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals, and the development of high-speed customized logic cells. Additional responsibilities in this role involves good understanding of functional and test mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization, 2.5D RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, physical verification (drc, lvs, antenna), debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex modem CPU Physical Design solutions from netlist and timing constraints to the final product.

Minimum Qualifications 
7+ years of experience in physical design for complex SoC or CPU devices
Proficient in place and route, floorplanning, power planning, IR drop analysis
Experienced in multi-mode & multi-corner (MMMC) techniques
Experienced in clock tree synthesis, routing, timing optimization, RC extraction
Experienced in signal integrity analysis, cross talk noise and delay analysis
Experienced in STA and debugging timing violations


Preferred Qualifications
12+ years industry experience in the Physical Design as outlined above
Place & Route tool experience on Cadence Innovus
STA experience using Synopsys Primetime for timing closure
Experience in Formal Verification
Experience in Physical Verification experience 
 
Education Requirements
Required: BSEE degree or related field. 
Preferred: MSEE degree or related field.
 
About Encore Semi:
Encore Semi is a successful Engineering Solutions company. We build Centers of Expertise to support our many customers from the semiconductor and electronics system industry in North America. Our teams of experts contribute to leading-edge projects in the areas of SoC design and embedded software. We provide high-value through acceleration, performance improvement, optimization, and risk mitigation.
Encore Semi provides its engineering team members with continuous exposure to top advanced technologies & tools, participation in challenging yet exciting projects, and direct collaboration with its industry-leading teams, customers, and long-term partners. Read about the company’s great benefits and career path in our website.
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