Job Openings | Encore Semi, Inc.

Sr Physical Design Engineer ( Onsite - Nashua NH) with Active Secret Clearance - Nashua, NH

Wed, 03 Jun 2026 15:48:11 GMT

Physical Design Engineer (ASIC/SoC) - Onsite
Clearance Requirement: Active Secret Clearance (or ability to obtain and maintain one)
About the Role
Are you ready to design the future of aerospace and defense technology? We are looking for a talented and highly motivated Physical Design Engineer to join our Advanced Microelectronics team. In this role, you will play a critical part in the development of next-generation ASICs and SoCs that power mission-critical systems.
Own the physical implementation of complex, high-performance, and low-power designs from netlist through GDSII tape-out. Working alongside a collaborative team of digital design, verification, and systems engineers, you will leverage industry-leading EDA tools to ensure our silicon meets the rigorous performance, power, and area (PPA) targets required for national security applications.
Key Responsibilities

Netlist-to-GDSII Execution: Drive block-level and chip-level physical implementation, including floorplanning, power grid design, placement, clock tree synthesis (CTS), and routing using Synopsys Fusion Compiler.
Timing Closure: Perform rigorous Static Timing Analysis (STA), constraint validation, and timing closure using Synopsys PrimeTime across multiple corners and operating modes.
Power & Reliability Analysis: Conduct dynamic and static IR-drop analysis, as well as Electromigration (EM) checks, using Ansys Redhawk to ensure robust power delivery and design reliability.
Physical Verification: Execute and debug Design Rule Checks (DRC) and Layout Versus Schematic (LVS) checks to ensure manufacturing compliance and flawless tape-outs.
Methodology Improvement: Collaborate with cross-functional teams to refine physical design methodologies, automate repetitive workflows using Tcl/Python, and optimize the overall PPA.

Required Qualifications

Clearance: Must be a U.S. Citizen with an Active U.S. Secret Clearance (or the ability to obtain and maintain one).
Education: Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
Experience: Proven industry experience in ASIC/SoC physical design and tape-out cycles.
Tool Proficiency: Hands-on expertise with Fusion Compiler (or equivalent place-and-route tools like IC Compiler II/Innovus).
- Deep knowledge of STA and sign-off timing closure using PrimeTime.
- Experience with EM/IR analysis using Redhawk.
- Proficiency in physical verification (DRC/LVS) sign-off tools (e.g., Calibre, IC Validator).
Scripting: Strong scripting skills in Tcl, Python, or Perl to automate EDA flows.

Problem Solving: Exceptional analytical skills and the ability to debug complex layout, timing, or integration issues autonomously.

The anticipated annual base salary for this position is between $170,000 to $210,000, which also includes a comprehensive benefits package.

Full-Time Benefits:
• 15 days of PTO per calendar year
• 10 paid Holidays per calendar year
• Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
• Dental & Vision: Company covers 50% of premiums for Employee and Dependents
• Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
• Employee Assistant Program (EAP)
• 401k - Traditional & Roth
• Life/AD&D and Long-Term Disability
• Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.

Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.

Sr Physical Design Engineer (Manassas, VA), Onsite with Active Secret Clearance - Manassas, VA

Wed, 03 Jun 2026 15:46:10 GMT

Netlist-to-GDSII Execution: Drive block-level and chip-level physical implementation, including floorplanning, power grid design, placement, clock tree synthesis (CTS), and routing using Synopsys Fusion Compiler.
Timing Closure: Perform rigorous Static Timing Analysis (STA), constraint validation, and timing closure using Synopsys PrimeTime across multiple corners and operating modes.
Power & Reliability Analysis: Conduct dynamic and static IR-drop analysis, as well as Electromigration (EM) checks, using Ansys Redhawk to ensure robust power delivery and design reliability.
Physical Verification: Execute and debug Design Rule Checks (DRC) and Layout Versus Schematic (LVS) checks to ensure manufacturing compliance and flawless tape-outs.
Methodology Improvement: Collaborate with cross-functional teams to refine physical design methodologies, automate repetitive workflows using Tcl/Python, and optimize the overall PPA.

Required Qualifications

Clearance: Must be a U.S. Citizen with an Active U.S. Secret Clearance (or the ability to obtain and maintain one).
Education: Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
Experience: Proven industry experience in ASIC/SoC physical design and tape-out cycles.
Tool Proficiency: Hands-on expertise with Fusion Compiler (or equivalent place-and-route tools like IC Compiler II/Innovus).
- Deep knowledge of STA and sign-off timing closure using PrimeTime.
- Experience with EM/IR analysis using Redhawk.
- Proficiency in physical verification (DRC/LVS) sign-off tools (e.g., Calibre, IC Validator).
Scripting: Strong scripting skills in Tcl, Python, or Perl to automate EDA flows.

Sr Design Verification Engineer (Austin TX - Onsite) - Austin, TX

Tue, 26 May 2026 20:12:41 GMT

Sr Design Verification Engineer (Remote)
Full-time: Salary + Benefits + Bonuses / Contractor
Work Status: US citizen or Lawful Permanent Resident.
Location: Austin TX

Digital ASIC Verification Engineer
We are looking for an experienced Digital ASIC Verification Engineer to verify complex digital systems, including ARM-based CPUs and DSP blocks. You will own the full verification lifecycle, from test planning to coverage closure using SystemVerilog and UVM.

Responsibilities

Develop UVM/SystemVerilog testbenches for block and system-level verification
Create and execute test plans; drive functional and code coverage closure
Automate test generation and regressions using Python and MATLAB
Support pre-silicon verification and post-silicon bring-up
Collaborate across teams to ensure design quality and integrity

Qualifications

10+ years of ASIC verification experience
Strong skills in SystemVerilog, UVM, and constrained random verification
Familiarity with ARM/CPU architecture and OOP concepts
Proficiency in Python scripting (MATLAB a plus)
Bachelors in EE/CS/CE (Master’s preferred)

The anticipated annual base salary for this position is between $150,000 to $165,000, which also includes a comprehensive benefits package.

Full-Time Benefits:
• 15 days of PTO per calendar year
• 10 paid Holidays per calendar year
• Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
• Dental & Vision: Company covers 50% of premiums for Employee and Dependents
• Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
• Employee Assistant Program (EAP)
• 401k - Traditional & Roth
• Life/AD&D and Long-Term Disability
• Tuition reimbursement

Equal Opportunity Policy Statement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.

Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.

LinkedIn :: https://www.linkedin.com/in/rtl2gds/

Sr Physical Design Engineer ( Remote) - Raleigh, NC

Fri, 22 May 2026 15:42:32 GMT

Sr Physical Design Engineer – Remote
Location: Remote – Anywhere in US
Full-time: Salary + Benefits + Bonuses / Contractor
Work Status: US citizen or Lawful Permanent Resident

Min. 10+ years of experience in 3 nm and/or 5 nm technology node.
Block and top-level P&R experience
Timing closure experience with Tempus and/or Primetime
Arm or similar embedded processor experience
Physical Verification experience
Knowledge of industry standard tools and flows Cadence, Synopsys, Siemens

The anticipated annual base salary for this position is between $140,000 to $165,000 which also includes a comprehensive benefits package.

Full-Time Benefits:
• 15 days of PTO per calendar year
• 10 paid Holidays per calendar year
• Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
• Dental & Vision: Company covers 50% of premiums for Employee and Dependents
• Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
• Employee Assistant Program (EAP)
• 401k - Traditional & Roth
• Life/AD&D and Long-Term Disability
• Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.

Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.

Sr Physical Design Engineer (Onsite) with Active Secret Clearance - Burlington, VT

Fri, 22 May 2026 15:39:40 GMT

Physical Design Engineer (ASIC/SoC) – with Active Secret Clearance
Clearance Requirement: Active Secret Clearance (or ability to obtain and maintain one)
Location : Onsite only in San Diego CA, Austin TX, Manassas VA or Nashua NH.
About the Role
Are you ready to design the future of aerospace and defense technology? We are looking for a talented and highly motivated Physical Design Engineer to join our Advanced Microelectronics team. In this role, you will play a critical part in the development of next-generation ASICs and SoCs that power mission-critical systems.
Own the physical implementation of complex, high-performance, and low-power designs from netlist through GDSII tape-out. Working alongside a collaborative team of digital design, verification, and systems engineers, you will leverage industry-leading EDA tools to ensure our silicon meets the rigorous performance, power, and area (PPA) targets required for national security applications.
Key Responsibilities

Netlist-to-GDSII Execution: Drive block-level and chip-level physical implementation, including floorplanning, power grid design, placement, clock tree synthesis (CTS), and routing using Synopsys Fusion Compiler.
Timing Closure: Perform rigorous Static Timing Analysis (STA), constraint validation, and timing closure using Synopsys PrimeTime across multiple corners and operating modes.
Power & Reliability Analysis: Conduct dynamic and static IR-drop analysis, as well as Electromigration (EM) checks, using Ansys Redhawk to ensure robust power delivery and design reliability.
Physical Verification: Execute and debug Design Rule Checks (DRC) and Layout Versus Schematic (LVS) checks to ensure manufacturing compliance and flawless tape-outs.
Methodology Improvement: Collaborate with cross-functional teams to refine physical design methodologies, automate repetitive workflows using Tcl/Python, and optimize the overall PPA.

Required Qualifications

Clearance: Must be a U.S. Citizen with an Active U.S. Secret Clearance (or the ability to obtain and maintain one).
Education: Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
Experience: Proven industry experience in ASIC/SoC physical design and tape-out cycles.
Tool Proficiency: Hands-on expertise with Fusion Compiler (or equivalent place-and-route tools like IC Compiler II/Innovus).
- Deep knowledge of STA and sign-off timing closure using PrimeTime.
- Experience with EM/IR analysis using Redhawk.
- Proficiency in physical verification (DRC/LVS) sign-off tools (e.g., Calibre, IC Validator).
Scripting: Strong scripting skills in Tcl, Python, or Perl to automate EDA flows.

Sr Physical Design Engineer ( Onsite) with Active Secret Cleance - Boston, MA

Fri, 22 May 2026 15:39:02 GMT

Netlist-to-GDSII Execution: Drive block-level and chip-level physical implementation, including floorplanning, power grid design, placement, clock tree synthesis (CTS), and routing using Synopsys Fusion Compiler.
Timing Closure: Perform rigorous Static Timing Analysis (STA), constraint validation, and timing closure using Synopsys PrimeTime across multiple corners and operating modes.
Power & Reliability Analysis: Conduct dynamic and static IR-drop analysis, as well as Electromigration (EM) checks, using Ansys Redhawk to ensure robust power delivery and design reliability.
Physical Verification: Execute and debug Design Rule Checks (DRC) and Layout Versus Schematic (LVS) checks to ensure manufacturing compliance and flawless tape-outs.
Methodology Improvement: Collaborate with cross-functional teams to refine physical design methodologies, automate repetitive workflows using Tcl/Python, and optimize the overall PPA.

Required Qualifications

Clearance: Must be a U.S. Citizen with an Active U.S. Secret Clearance (or the ability to obtain and maintain one).
Education: Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
Experience: Proven industry experience in ASIC/SoC physical design and tape-out cycles.
Tool Proficiency: Hands-on expertise with Fusion Compiler (or equivalent place-and-route tools like IC Compiler II/Innovus).
- Deep knowledge of STA and sign-off timing closure using PrimeTime.
- Experience with EM/IR analysis using Redhawk.
- Proficiency in physical verification (DRC/LVS) sign-off tools (e.g., Calibre, IC Validator).
Scripting: Strong scripting skills in Tcl, Python, or Perl to automate EDA flows.

Sr Physical Design Engineer (Remote) - Chandler, AZ

Fri, 22 May 2026 15:38:18 GMT

Sr Physical Design Engineer – Remote
Location: Remote – Anywhere in US
Full-time: Salary + Benefits + Bonuses / Contractor
Work Status: US citizen or Lawful Permanent Resident

Min. 10+ years of experience in 3 nm and/or 5 nm technology node.
Block and top-level P&R experience
Timing closure experience with Tempus and/or Primetime
Arm or similar embedded processor experience
Physical Verification experience
Knowledge of industry standard tools and flows Cadence, Synopsys, Siemens

Sr Physical Design Engineer (Remote) - Raleigh, NC

Fri, 22 May 2026 15:35:01 GMT

Sr Physical Design Engineer – Remote
Location: Remote – Anywhere in US
Full-time: Salary + Benefits + Bonuses / Contractor
Work Status: Must be US citizen or Lawful Permanent Resident.

Min. 10+ years of experience in 3 nm and/or 5 nm technology node.
Block and top-level P&R experience
Timing closure experience with Tempus and/or Primetime
Arm or similar embedded processor experience
Physical Verification experience
Knowledge of industry standard tools and flows Cadence, Synopsys, Siemens

Sr Physical Design Engineer (Remote) - Burlington, VT

Fri, 22 May 2026 15:34:08 GMT

Sr Physical Design Engineer – Remote
Location: Remote – Anywhere in US
Full-time: Salary + Benefits + Bonuses / Contractor
Work Status: Must be US citizen or Lawful Permanent Resident.

Min. 10+ years of experience in 3 nm and/or 5 nm technology node.
Block and top-level P&R experience
Timing closure experience with Tempus and/or Primetime
Arm or similar embedded processor experience
Physical Verification experience
Knowledge of industry standard tools and flows Cadence, Synopsys, Siemens

Sr Physical Design Engineer ( Austin TX - Onsite) - Austin, TX

Fri, 22 May 2026 15:33:31 GMT

Netlist-to-GDSII Execution: Drive block-level and chip-level physical implementation, including floorplanning, power grid design, placement, clock tree synthesis (CTS), and routing using Synopsys Fusion Compiler.
Timing Closure: Perform rigorous Static Timing Analysis (STA), constraint validation, and timing closure using Synopsys PrimeTime across multiple corners and operating modes.
Power & Reliability Analysis: Conduct dynamic and static IR-drop analysis, as well as Electromigration (EM) checks, using Ansys Redhawk to ensure robust power delivery and design reliability.
Physical Verification: Execute and debug Design Rule Checks (DRC) and Layout Versus Schematic (LVS) checks to ensure manufacturing compliance and flawless tape-outs.
Methodology Improvement: Collaborate with cross-functional teams to refine physical design methodologies, automate repetitive workflows using Tcl/Python, and optimize the overall PPA.

Required Qualifications

Clearance: Must be a U.S. Citizen with an Active U.S. Secret Clearance (or the ability to obtain and maintain one).
Education: Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
Experience: Proven industry experience in ASIC/SoC physical design and tape-out cycles.
Tool Proficiency: Hands-on expertise with Fusion Compiler (or equivalent place-and-route tools like IC Compiler II/Innovus).
- Deep knowledge of STA and sign-off timing closure using PrimeTime.
- Experience with EM/IR analysis using Redhawk.
- Proficiency in physical verification (DRC/LVS) sign-off tools (e.g., Calibre, IC Validator).
Scripting: Strong scripting skills in Tcl, Python, or Perl to automate EDA flows.

Sr Physical Design Engineer ( Remote) - Irvine, CA

Fri, 22 May 2026 15:32:31 GMT

Netlist-to-GDSII Execution: Drive block-level and chip-level physical implementation, including floorplanning, power grid design, placement, clock tree synthesis (CTS), and routing using Synopsys Fusion Compiler.
Timing Closure: Perform rigorous Static Timing Analysis (STA), constraint validation, and timing closure using Synopsys PrimeTime across multiple corners and operating modes.
Power & Reliability Analysis: Conduct dynamic and static IR-drop analysis, as well as Electromigration (EM) checks, using Ansys Redhawk to ensure robust power delivery and design reliability.
Physical Verification: Execute and debug Design Rule Checks (DRC) and Layout Versus Schematic (LVS) checks to ensure manufacturing compliance and flawless tape-outs.
Methodology Improvement: Collaborate with cross-functional teams to refine physical design methodologies, automate repetitive workflows using Tcl/Python, and optimize the overall PPA.

Required Qualifications

Clearance: Must be a U.S. Citizen with an Active U.S. Secret Clearance (or the ability to obtain and maintain one).
Education: Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
Experience: Proven industry experience in ASIC/SoC physical design and tape-out cycles.
Tool Proficiency: Hands-on expertise with Fusion Compiler (or equivalent place-and-route tools like IC Compiler II/Innovus).
- Deep knowledge of STA and sign-off timing closure using PrimeTime.
- Experience with EM/IR analysis using Redhawk.
- Proficiency in physical verification (DRC/LVS) sign-off tools (e.g., Calibre, IC Validator).
Scripting: Strong scripting skills in Tcl, Python, or Perl to automate EDA flows.

Sr Physical Design Engineer (San Diego CA - Onsite ) with Active Secret Clearance - San Diego, CA

Fri, 22 May 2026 15:32:00 GMT

Netlist-to-GDSII Execution: Drive block-level and chip-level physical implementation, including floorplanning, power grid design, placement, clock tree synthesis (CTS), and routing using Synopsys Fusion Compiler.
Timing Closure: Perform rigorous Static Timing Analysis (STA), constraint validation, and timing closure using Synopsys PrimeTime across multiple corners and operating modes.
Power & Reliability Analysis: Conduct dynamic and static IR-drop analysis, as well as Electromigration (EM) checks, using Ansys Redhawk to ensure robust power delivery and design reliability.
Physical Verification: Execute and debug Design Rule Checks (DRC) and Layout Versus Schematic (LVS) checks to ensure manufacturing compliance and flawless tape-outs.
Methodology Improvement: Collaborate with cross-functional teams to refine physical design methodologies, automate repetitive workflows using Tcl/Python, and optimize the overall PPA.

Required Qualifications

Clearance: Must be a U.S. Citizen with an Active U.S. Secret Clearance (or the ability to obtain and maintain one).
Education: Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
Experience: Proven industry experience in ASIC/SoC physical design and tape-out cycles.
Tool Proficiency: Hands-on expertise with Fusion Compiler (or equivalent place-and-route tools like IC Compiler II/Innovus).
- Deep knowledge of STA and sign-off timing closure using PrimeTime.
- Experience with EM/IR analysis using Redhawk.
- Proficiency in physical verification (DRC/LVS) sign-off tools (e.g., Calibre, IC Validator).
Scripting: Strong scripting skills in Tcl, Python, or Perl to automate EDA flows.

Sr Physical Design Engineer ( Remote) - Redmond, WA

Fri, 22 May 2026 15:31:21 GMT

Sr Physical Design Engineer – Remote
Location: Remote – Anywhere in US
Full-time: Salary + Benefits + Bonuses / Contractor
Work Status: Must be US citizen or Lawful Permanent Resident.

Min. 10+ years of experience in 3 nm and/or 5 nm technology node.
Block and top-level P&R experience
Timing closure experience with Tempus and/or Primetime
Arm or similar embedded processor experience
Physical Verification experience
Knowledge of industry standard tools and flows Cadence, Synopsys, Siemens

Sr IC Layout Designer ( Sunnyvale CA - Onsite) - Sunnyvale, CA

Mon, 23 Mar 2026 11:46:36 GMT

POSITION DETAILS:
You will be part of the Encore Semi design and circuit layout team, creating next generation products for commercial, civil and space missions. You will work as part of a team with the RFIC/Mixed Signal Designers and Layout Designers on chip layout and custom analog and RFIC IP blocks in technologies down to 3 nm.

Location: 100% on-site in Redmond WA
Full-time: Salary + Benefits + Bonuses / Contractor
Work Status: Must be US citizen or Lawful Permanent Resident.

Responsibilities:
Working with IC designers and chip leads to determine the chip and block floorplan, including strategies for power and ground distribution.
Performing layout of custom RF and analog circuit blocks with attention to matching and minimizing parasitics in the layout.
Accurately estimating the schedule for the layout work and identifying areas of complexity that needs early investigation.
Performing DRC, ERC and LVS checks and resolving errors.

Key Qualifications:

Strong analog layout skills.
Expert-level knowledge with Cadence Virtuoso tool suite.
Expert-level knowledge with Mentor Graphics Calibre.
Strong experience in advanced node IC layout, must have experience in 7 nm (FinFET) or below.
The ideal candidate has experience with TSMC 3/4/5nm technology.
Experience with layout of analog blocks ADC / DAC / PLLs.
Experience with 112G SerDes layout a plus.
Understand layout considerations for device matching, coupling and noise isolation.

The anticipated annual base salary for this position is between $130,000 to $160,000, which also includes a comprehensive benefits package.

Full-Time Benefits:
• 15 days of PTO per calendar year
• 10 paid Holidays per calendar year
• Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
• Dental & Vision: Company covers 50% of premiums for Employee and Dependents
• Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
• Employee Assistant Program (EAP)
• 401k - Traditional & Roth
• Life/AD&D and Long-Term Disability
• Tuition reimbursement

Equal Opportunity Policy Statement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.

Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.

Sr IC Layout Designer ( Onsite - Irvine CA) - Irvine, CA

Mon, 23 Mar 2026 11:45:54 GMT

POSITION DETAILS:
You will be part of the Encore Semi design and circuit layout team, creating next generation products for commercial, civil and space missions. You will work as part of a team with the RFIC/Mixed Signal Designers and Layout Designers on chip layout and custom analog and RFIC IP blocks in technologies down to 3 nm.

Location: 100% on-site in Irvine CA
Full-time: Salary + Benefits + Bonuses / Contractor
Work Status: Must be US citizen or Lawful Permanent Resident.

Responsibilities:
Working with IC designers and chip leads to determine the chip and block floorplan, including strategies for power and ground distribution.
Performing layout of custom RF and analog circuit blocks with attention to matching and minimizing parasitics in the layout.
Accurately estimating the schedule for the layout work and identifying areas of complexity that needs early investigation.
Performing DRC, ERC and LVS checks and resolving errors.

Key Qualifications:

Strong analog layout skills.
Expert-level knowledge with Cadence Virtuoso tool suite.
Expert-level knowledge with Mentor Graphics Calibre.
Strong experience in advanced node IC layout, must have experience in 7 nm (FinFET) or below.
The ideal candidate has experience with TSMC 3/4/5nm technology.
Experience with layout of analog blocks ADC / DAC / PLLs.
Experience with 112G SerDes layout a plus.
Understand layout considerations for device matching, coupling and noise isolation.

Sr IC layout Designer (Redmond, WA - Onsite) - Redmond, WA

Mon, 23 Mar 2026 11:44:59 GMT

Strong analog layout skills.
Expert-level knowledge with Cadence Virtuoso tool suite.
Expert-level knowledge with Mentor Graphics Calibre.
Strong experience in advanced node IC layout, must have experience in 7 nm (FinFET) or below.
The ideal candidate has experience with TSMC 3/4/5nm technology.
Experience with layout of analog blocks ADC / DAC / PLLs.
Experience with 112G SerDes layout a plus.
Understand layout considerations for device matching, coupling and noise isolation.

Sr Design Verification Engineer ( Redmond WA - Onsite) - Redmond, WA

Mon, 23 Mar 2026 11:38:58 GMT

Sr Design Verification Engineer (Remote)
Full-time: Salary + Benefits + Bonuses / Contractor
Work Status: US citizen or Lawful Permanent Resident.
Location: Redmond WA

Digital ASIC Verification Engineer
We are looking for an experienced Digital ASIC Verification Engineer to verify complex digital systems, including ARM-based CPUs and DSP blocks. You will own the full verification lifecycle, from test planning to coverage closure using SystemVerilog and UVM.

Responsibilities

Develop UVM/SystemVerilog testbenches for block and system-level verification
Create and execute test plans; drive functional and code coverage closure
Automate test generation and regressions using Python and MATLAB
Support pre-silicon verification and post-silicon bring-up
Collaborate across teams to ensure design quality and integrity

Qualifications

10+ years of ASIC verification experience
Strong skills in SystemVerilog, UVM, and constrained random verification
Familiarity with ARM/CPU architecture and OOP concepts
Proficiency in Python scripting (MATLAB a plus)
Bachelors in EE/CS/CE (Master’s preferred)

Sr Design Verification Engineer ( Irvine CA - Onsite) - Irvine, CA

Mon, 23 Mar 2026 11:37:48 GMT

Sr Design Verification Engineer (Remote)
Full-time: Salary + Benefits + Bonuses / Contractor
Work Status: US citizen or Lawful Permanent Resident.
Location: Irvine CA

Digital ASIC Verification Engineer
We are looking for an experienced Digital ASIC Verification Engineer to verify complex digital systems, including ARM-based CPUs and DSP blocks. You will own the full verification lifecycle, from test planning to coverage closure using SystemVerilog and UVM.

Responsibilities

Develop UVM/SystemVerilog testbenches for block and system-level verification
Create and execute test plans; drive functional and code coverage closure
Automate test generation and regressions using Python and MATLAB
Support pre-silicon verification and post-silicon bring-up
Collaborate across teams to ensure design quality and integrity

Qualifications

10+ years of ASIC verification experience
Strong skills in SystemVerilog, UVM, and constrained random verification
Familiarity with ARM/CPU architecture and OOP concepts
Proficiency in Python scripting (MATLAB a plus)
Bachelors in EE/CS/CE (Master’s preferred)

Sr Design Verification Engineer ( Sunnyvale CA - Onsite ) - Sunnyvale, CA

Mon, 23 Mar 2026 11:37:05 GMT

Sr Design Verification Engineer
Full-time: Salary + Benefits + Bonuses / Contractor
Work Status: US citizen or Lawful Permanent Resident.
Location: Sunnyvale CA

Digital ASIC Verification Engineer
We are looking for an experienced Digital ASIC Verification Engineer to verify complex digital systems, including ARM-based CPUs and DSP blocks. You will own the full verification lifecycle, from test planning to coverage closure using SystemVerilog and UVM.

Responsibilities

Develop UVM/SystemVerilog testbenches for block and system-level verification
Create and execute test plans; drive functional and code coverage closure
Automate test generation and regressions using Python and MATLAB
Support pre-silicon verification and post-silicon bring-up
Collaborate across teams to ensure design quality and integrity

Qualifications

10+ years of ASIC verification experience
Strong skills in SystemVerilog, UVM, and constrained random verification
Familiarity with ARM/CPU architecture and OOP concepts
Proficiency in Python scripting (MATLAB a plus)
Bachelors in EE/CS/CE (Master’s preferred)