Job Title
Senior Synthesis Engineer
Senior Layout Design Engineer
Senior DFT Engineer
Senior Static Timing Analysis (STA) Engineer
Senior SerDes Circuit Design Engineer
Technical Lead - SerDes Architect
Senior Physical Design Engineer
Senior Design Verification (sub-system level) Engineer
Senior Design Verification (chip-level) Engineer
Job Title
Senior Synthesis Engineer
Senior Layout Design Engineer
Senior DFT Engineer
Senior Static Timing Analysis (STA) Engineer
Senior SerDes Circuit Design Engineer
Technical Lead - SerDes Architect
Senior Physical Design Engineer
Senior Design Verification (sub-system level) Engineer
Senior Design Verification (chip-level) Engineer
Job Title
Senior Synthesis Engineer
Senior Layout Design Engineer
Senior DFT Engineer
Senior Static Timing Analysis (STA) Engineer
Senior ASIC Design Engineer
Senior RTL Design Engineer
Senior FPGA Design Engineer
Technical Lead - SerDes Architect
Senior Physical Design Engineer
Senior Design Verification (chip-level) Engineer
Senior Design Verification (sub-system level) Engineer
Job Title
Senior Synthesis Engineer
Senior Layout Design Engineer
Senior DFT Engineer
Senior Static Timing Analysis (STA) Engineer
Senior SerDes Circuit Design Engineer
Technical Lead - SerDes Architect
Senior Physical Design Engineer
Senior Design Verification (chip-level) Engineer
Senior Design Verification (sub-system level) Engineer
Job Title
Senior Synthesis Engineer
Senior Layout Design Engineer
Senior DFT Engineer
Senior Static Timing Analysis (STA) Engineer
Senior Digital Design Engineer
Senior ASIC Design Engineer
Senior FPGA Design Engineer
Senior RTL Design Engineer
Senior SerDes Circuit Design Engineer
Technical Lead - SerDes Architect
Senior Physical Design Engineer
Senior Design Verification (chip-level) Engineer
Senior Design Verification (sub-system level) Engineer
Director of SoC Engineering
Job Title
Senior Synthesis Engineer
Senior Layout Design Engineer
Senior DFT Engineer
Senior Static Timing Analysis (STA) Engineer
Senior ASIC Design Engineer
Senior RTL Design Engineer
Senior FPGA Design Engineer
Technical Lead - SerDes Architect
Senior Physical Design Engineer
Senior Design Verification (chip-level) Engineer
Senior Design Verification (sub-system level) Engineer
Job Title
Senior Synthesis Engineer
Senior Layout Design Engineer
Senior DFT Engineer
Senior Static Timing Analysis (STA) Engineer
Senior SerDes Circuit Design Engineer
Technical Lead - SerDes Architect
Senior Physical Design Engineer
Senior Design Verification (chip-level) Engineer
Senior Design Verification (sub-system level) Engineer
Job Title
Senior Synthesis Engineer
Senior Layout Design Engineer
Senior DFT Engineer
Senior Static Timing Analysis (STA) Engineer
Senior ASIC Design Engineer
Senior FPGA Design Engineer
Senior RTL Design Engineer
Technical Lead - SerDes Architect
Senior Physical Design Engineer
Senior Design Verification (chip-level) Engineer
Senior Design Verification (sub-system level) Engineer
Job Title
Senior Synthesis Engineer
Senior Layout Design Engineer
Senior DFT Engineer
Senior Static Timing Analysis (STA) Engineer
Senior Physical Design Engineer
Senior Digital Design Engineer
Senior ASIC Design Engineer
Senior RTL Design Engineer
Senior FPGA Design Engineer
Senior SerDes Circuit Design Engineer
Technical Lead - SerDes Architect
Senior Physical Design Engineer
Senior Design Verification (chip-level) Engineer
Senior Design Verification (sub-system level) Engineer
Director of SoC Engineering
Job Title
Senior Synthesis Engineer
Senior Layout Design Engineer
Senior DFT Engineer
Senior Static Timing Analysis (STA) Engineer
Senior Digital Design Engineer
Senior ASIC Design Engineer
Senior RTL Design Engineer
Senior FPGA Design Engineer
Technical Lead - SerDes Architect
Senior Physical Design Engineer
Senior Design Verification (chip-level) Engineer
Senior Design Verification (sub-system level) Engineer
Director of SoC Engineering