Position Title: Senior FPGA Verification Engineer
Location: Melbourne, FL
About the Team:
Join the growing Encore Semi Front-End Development team to collaborate with module level architects and FPGA designers to Functionally Verify new complex FPGA designs. Building on your background of FPGA / ASIC Verification, you would join a team developing advanced FPGA designs for various applications.
About the Project:
As a senior member of an FPGA development team, you would be responsible for building SV/UVM Verification environments, putting together module and “full-chip” Verification plans and executing against those plans to deliver functionally correct designs. If you have a background in FPGA Verification, joining the Encore Semi Front-End Development team could be for you.
• 5+ years of experience in Verification of advanced FPGAs
• US citizenship is required due to the nature of the project and facility
• Experience with modern SV/UVM based Verification environments including agents, scoreboards, coverage, and randomization
• Experience with simulation environments required – Cadence Incisive experience would be a plus
• Experience with the full FPGA Verification flow from Verification environment development, testplanning, test execution and debug
• Experience with FPGA development environments from Xilinx (Vivado) or Intel/Altera (Quartus)
• Verification experience with high speed serial interfaces such as Ethernet, PCIe, sRIO, Fibre Channel
• Experience connecting FPGAs to DDR memory
• Required: Bachelor's, Electrical Engineering
• Preferred: Master's, Electrical Engineering