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Senior RTL/Logic Design Engineer (must have a Secret Security Clearance)

Scottsdale, AZ
Position Title: ASIC / SOC RTL / Logic Design Engineer
Location: Scottsdale, CA
Status: Full-time
 
About the Team:
Join the growing Encore Semi Front-End Development team to collaborate with architects and other designers to define the microarchitecture and RTL code for complex custom ASIC / SOCs.  Building on your background in RTL development, you would join a team designing advanced ASIC / SOCs.
 
About the Project:
As a senior member of the development team, you would define the microarchitecture based on specifications and legacy designs and code RTL to implement those designs.  You would build simulatable versions of the designs and work with Verification engineers to create functionally correct designs and do preliminary synthesis to ensure a smooth transition to the design execution phase.  If you have a background in Logic Design / RTL coding of custom designs, joining the Encore Semi Front-End Development team could be for you.
 
Minimum Qualifications:
• Due to the nature of the team you will be collaborating with, a Department of Defense Secret Security Clearance is REQUIRED. Engineers with a clearance in the past 2 years will be preferred.  US citizenship is a requirement.
• Experience with Verilog RTL coding of complex custom ASICs and SOCs
• Experience defining the microarchitecture of a complex design based on specifications as well as adapting and enhancing legacy designs
• Experience with simulation environments from Synopsys or Cadence (or both)
• Experience with logic synthesis
• 5+ years of experience in Logic Design
 
Preferred Qualifications:
• Experience with Logic Design of custom / proprietary interfaces, cache hierarchies or RISC cores would be beneficial
• Working on designs with multiple power / voltage islands including experience with designing and implementing UPF designs a plus
 
Education Requirements:
• Required: Bachelor's, Electrical Engineering
• Preferred: Master's, Electrical Engineering
 
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