Position Title: Analog/Mixed-Signal IC Layout Designer
Location: Phoenix, AZ
Status: Full-time (salary + benefits + bonuses)
About the Project:
Encore Semi is assembling a team of well-rounded analog and mixed-signal IC layout engineers to support long-term needs of its customers. The engineers will be involved in block-level layout and chip-level integration efforts using planar and advanced FinFET technology nodes for a multitude of applications.
We seek engineers at all levels of experience with opportunity for training, technical leadership and management as the team grows organically.
• Experience with a plurality of planar CMOS technologies and below and/or FinFET.
• Experience with the layout of analog and mixed-signal blocks such as ADC’s and DAC’s, filters, op-amps, bias and reference generators, supply regulators; And/Or,
• Experience with the layout of SerDes blocks and systems such as T-coils, CTLE’s, DFE’s, PLL’s, serializers/de-serializers, analog equalizers and clock distribution circuits.
• Experience with Cadence and Mentor suite of design tools (Virtuoso Schematic and Layout, Voltus-Fi, Caliber, etc.).
• Ability to work in close collaboration with the designers to achieve a fully optimized layout and with other layout engineers for seamless top-level integration.
• Good understanding of engineering principles, such as matching, shielding, KVL/KCL, etc.
• Good knowledge of device reliability mechanisms, electromigration, latch-up, guard-rings, DNW, IO-Ring building, STI, ESD, parasitics optimization and advanced process effects such as LOD and LDE.
• Candidates considered for senior and technical leadership roles need to demonstrate extensive experience integrating and verifying complex SOC projects, mentoring junior engineers and establishing layout workflow and methodology to ensure high quality and first-time success. Experience with managing layout resources to meet schedules and ensuring accountability, is desirable.
• Number of years of experience: 5 to 15 years