Position Title: Senior Design Verification Engineer
Location: Menlo Park, CA (work from home during CA stay-at-home order)
Status: Full-time (salary + benefits + bonuses)
About the Team:
Join the growing Encore Semi Front-End Development team to collaborate with customers to design, and verify ASICs and FPGAs targeting next generation applications. Building on your background of Functional Verification, you would join a team verifying advanced features at the block and full-chip.
About the Project:
As a senior member of an SOC development team, you would be responsible for driving the Design Verification of either blocks (units) or full-chip elements of innovative ASIC designs or blocks within FPGAs. You will leverage your Functional Verification experience to develop Verification plans, create environments and tests to stress the correctness and effectiveness of features with an emphasis on multi-CPU implementation. If you have SOC Verification experience building OVM/UVM-based environments and stimulus, directing random testing and deploying a coverage-based approach, joining the Encore Semi Verification team could be for you.
• Functional Design Verification of logic blocks within an ASIC or FPGA including creation of the testbench / verification infrastructure, writing tests and driving functional coverage and debugging failures.
• Experience with SV for Verification as well as experience with modern Verification environments such as UVM, OVM or similar.
• Knowledge of other languages used in Verification which could include C/C++ tests or scripting languages such as Python
• 5+ years of experience as a Verification Engineer
• Experience in verification of specific functional blocks which could include DSP, Audio, Video, Graphics or interfaces.
• Experience moving beyond functional verification to analyzing performance based on testing in a simulation environment.
• Required: Bachelor's, Electrical Engineering
• Preferred: Master's, Electrical Engineering