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Senior FPGA Prototyping Engineer (must have an active Secret Security Clearance)

Scottsdale, AZ
Position Title: Senior FPGA Prototyping Engineer
Location: Scottsdale, AZ
Status: Full-time

About the Team:
The growing Encore Semi Front-End Development team collaborates with customers to design and verify SOCs and IPs targeting advanced applications.  Building on your background in Verification or Validation, you would join a team to enable next generation functionally correct designs and systems.

About the Project:
As a member of the Platform development team, you would enable FPGA Prototyping systems for next generation SOCs targeting advanced data processing and sensor systems.  The FPGA prototypes would be a platform to enable Functional Verification and pre-silicon Firmware Development.  You would drive mapping and partitioning the design to fit into FPGA prototyping systems as well as converting structures in the design (such as Memories and Analog blocks) to models which would efficiently map to an FPGA.  You would work with a wide range of team members including Verification and Validation Engineers as well as Firmware Developers.

Minimum Qualifications:
• Due to the nature of the team you will be collaborating with, US Citizenship and a Department of Defense Secret Security Clearance is required
• Experience creating and delivering FPGA Prototype platforms (similar to Synopsys HAPS).  Experience mapping and partitioning IP and SOC designs to FPGAs and working hands-on in the lab with such systems
• RTL coding experience (Verilog (preferred) or VHDL) in order to map RTL constructs to feature better suited for FPGAs.  Also, experience with FPGA development tools (such as Vivado or Synplify) would be valuable
• Scripting (Perl / Python) skills
• 5+ years of experience in CPU / SOC development with a focus on FPGA prototyping or Emulation enabling

Preferred Qualifications:
• Experience working with Xilinx development boards and implementing Verilog coded designs onto the FPGAs and peripherals on those boards
• Design Verification experience such as development of SV/UVM environments or execution of DV plans using SV/UVM simulation environments
• Experience with development of SOCs doing data processing, integration and analysis from multiple high performance sensors

Education Requirements:
• Required: Bachelor's, Electrical Engineering
• Preferred: Master's, Electrical Engineering
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