Position Title: ASIC / SOC Design Verification Engineer
Location: Scottsdale, AZ
Status: Full-time (salary + benefits + bonuses)
About the Team:
Join the growing Encore Semi Front-End Development team to collaborate with Microarchitects and logic developers to Functionally verify complex custom designed ASICs and SOCs. Building on your background of Design Verification, you would join a team developing advanced ASIC / SOC designs.
About the Project:
As a senior member of the development team, you would architect and build SV/UVM based Verification environments. In many cases, you could be updating and adapting Verification environments from legacy designs into a more modern approach utilizing current generation SV/UVM techniques. These environments and the Verification plan you develop will be used as the design move from a preliminary to the execution phase to complete Verification execution. If you have a background in Design Verification of custom designs, joining the Encore Semi Front-End Development team could be for you.
• Due to the nature of the team you will be collaborating with, a Department of Defense Secret Security Clearance is REQUIRED. Engineers with a clearance in the past 2 years will be preferred. US citizenship is a Requirement.
• Experience with modern SV/UVM based Verification environments including agents, scoreboards, coverage and randomization will be required. The experience needs to go beyond usage of environments to being able to build such environments from scratch
• Verification experience at both the “full-chip” SOC and Unit / IP level is desired – especially utilizing Unit environments as part of a full-chip solution
• Experience with simulation / Verification environments from Synopsys or Cadence (or both)
• 5+ years of experience verifying complex, custom ASICs
• Experience with Verification of custom / proprietary interfaces, cache hierarchies or RISC cores would be beneficial
• Working on designs with multiple power / voltage islands including experience with UPF modeling and verification of such design is a plus
• Verification using tests in both SV/UVM environments as well as C/C++ or Assembly language
• Required: Bachelor's, Electrical Engineering
• Preferred: Master's, Electrical Engineering