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Principal SOC / PCIe Design Verification Engineer

Santa Clara, CA
Position Title: Principal SOC / PCIe Design Verification Engineer
Location: Santa Clara, CA or Remote/work from home
Status: Full-time (salary + benefits + bonuses)

About the Project:
As a SOC DV Engineer with a focus on High Speed and Coherent IO verification, you will work to understand the internal requirements and complexities of an SOC system and architect the required verification strategy. You will help set up methodologies, come up with test plans, and verify that the design meets the highest quality standards. We believe in early involvement of DV, so you will also participate in architecture/product definition through early involvement in the product life-cycle. In this role you will:
• Define entire verification architecture for all system memory coherency aspects
• Deep dive into microarchitecture of all agents and subsystems involved with system coherency
• Define verification architecture, develop test plans and build verification environment
• Work with design team to understand design intent and bring up verification plans and schedules
• Verify Subsystems and Full SoC using advanced verification methodologies
• Build agents and checkers from scratch. Perform and write test plan from design architecture specs and/or protocol standard
• Debug test cases and report verification result to achieve expected code/functional coverage goal
• Assist in emulation, FPGA, prototyping efforts
• Assist in silicon bring-up, debug and characterization
• Desired Areas of Expertise:
• ARM IPs (SMMU, GIC) and AMBA specs (AXI, AHB, APB)
• Experience with integrating peripheral controllers (I2C/SMBus, I3C, SPI/ QSPI, LPC/eSPI)
• PCIe controller integration
• Padring, GPIO design and integration
• UPF flow ownership
• Fabric experience
• CoreSight experience is a plus

Minimum Qualifications:
• BA/BS degree in Electrical Engineering with 10+ years of practical experience
• Strong fundamentals in digital ASIC verification
• Strong understanding of PCIe and one or more coherent IO protocols like CCIX and CXL
• Strong programmable language experience is required (one or more of Verilog, SystemVerilog, Perl, Python, Tcl Scripts, Makefile and/or C++)

Preferred Qualifications:
• MS degree in Electrical Engineering; 15 years of practical experience
• Expertise in the verification of PCIe controllers and subsystems
• Full stack PCIe exposure (PHY, datalink, transaction)
• Strong understanding of PCIe ordering rules in a multi-core system
• Exposure to CXL, CCIX or similar Coherent IO protocol
• A good understanding of the complete verification life cycle (test plan, testbench through coverage closure)
• Extensive knowledge in multiple testbench structures
• Knowledge of FPGA and emulation platforms
• Proficiency in UVM, C/C++
• Experience w/ PSS or higher level test construction languages
• Knowledge of assertion-based formal verification
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