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Senior Low Power Design Verification Engineer

Menlo Park, CA
Position Title: Low Power Design Verification Engineer
Locations: Menlo Park, CA or remote/work from home within USA
Full-time: Salary + Benefits + Bonuses

About the Team:
Join the growing Encore Semi Front-End Development team to collaborate with customers to design, and verify ASICs and FPGAs targeting next generation applications.  Building on your background of Design Verification and Low Power Design, you would join a team verifying advanced features at the block and full-chip.

About the Project:
As a senior member of an SOC development team, you would be responsible for driving the Design Verification with a focus on Low Power Design Verification. You will leverage your Design Verification experience to develop testplans, create environments and implement scoreboards and checkers with the goal of achieving 100% functional code and power coverage. You would work closely with designers, micro architects and firmware to resolve issues and bugs.

Minimum Qualifications:
• 7+ years of proven experience as a DV engineer with hands-on experience in Coverage Driven verification
• Hands on experience with SystemVerilog and UVM
• Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive simulators
• In depth experience with UPF based simulation flows
• 2+ Years of experience with C/C++
• BSEE

Preferred Qualifications:
• Experience with Power and Performance modeling using C, SystemC, or MATLAB
• Experience with both static (i.e. Synopsys VC LP) and dynamic (i.e. Synopsys VCS NLP) power-aware verification flows
• MSEE
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