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Senior SoC RTL/Logic Design Engineer

Austin, TX
Position Title: Senior SoC RTL/Logic Design Engineer
Locations: Austin or remote/work from home
Full-time: Salary + Benefits + Bonuses

About the Project:
As a member of the CPU SOC development team, you will work with the chip architects and other logic designers to define the interface / system microarchitecture, implement new IPs for the interfaces and integrate those, as well as some 3rd party IPs, into the overall SOC.  Areas of focus could include system elements such as Memory Management of multi-core/multi-die interrupt handling, PCIe controller integration or various peripheral interfaces.  Once created, you will work with Verification and Physical Design engineers to ensure the designs are functionally correct as well as do synthesis and preliminary physical design tasks to enable the tapeout of the overall SOC.  If you have a background in Logic Development and RTL coding of custom designs, joining the Encore Semi Front-End Development team could be for you.

Desired Areas of Expertise:
• ARM IPs (SMMU, GIC) and AMBA specs (AXI, AHB, APB)
• Experience with integrating peripheral controllers (I2C/SMBus, I3C, SPI/ QSPI, LPC/eSPI)
• PCIe controller integration
• Padring, GPIO design and integration
• UPF flow ownership
• Fabric experience
• CoreSight experience is a plus

Minimum Qualifications:
• Microarchitecture definition and RTL coding experience with SOC interconnect such as the AMBA interconnects (AXI, AHB, APB), external interfaces such as PCIe, SPI, I2C or System Memory Management or Global Interrupt handling
• Experience creating RTL for integrating various IPs into a larger SOC
• Experience coding RTL with low power in mind (such understanding of UPF flows) 
• Experience with at least one of the following functions: MMU, PCIe, Cache, Fabric or NoC, High Speed I/O
• Minimum of 5+ years of experience in Logic Design of complex, custom ASICs

Preferred Qualifications:
• ARM infrastructure experience with AMBA internal interconnects (AMBA – AXI, etc) or ARM system elements such as SMMU or GIC.
• Experience coding and integrating high performance CPU interconnect fabrics for multi-core and multi-die systems
• Knowledge of implementing SOC-wide Debug / Trace handling such as CoreSight
• Strong debugging experience with PCIe protocols
• Experience beyond RTL coding including integration to the larger SOC system, synthesis and gate level simulation

Education Requirements:
• Required: Bachelor of Science, Electrical Engineering (BSEE)
• Preferred: Master of Science, Electrical Engineering (MSEE)
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