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Senior Design Verification Infrastructure and Methodology Engineer 

Santa Clara, CA
Job Title: Senior Design Verification Infrastructure and Methodology Engineer 
Locations: Santa Clara, CA or remote/work from home
Full-time: Salary + Benefits + Bonuses

Summary:
As a Design Verification Infrastructure and Methodology Engineer, you will work with the DV, Design and CAD teams to build up robust automation systems for the entire design process.  You will leverage state-of-the-art tools to build a robust and efficient design process that enables us to build complex chip designs.

Responsibilities:
• Develop wrappers and automation around EDA tool workflows
• Drive and support source control, code review and continuous integration flows
• Build and support testbench automation, regression, and coverage collection flows
• Develop and maintain design and verification progress dashboards
• Build design-construction automation and code generators
• Interface to DRM grid management facilities for day-to-day use and regressions
• Build emulation resource sharing facilities
• Work w/ emulation team to automate build-and-test workflows
• Own block, full chip, and emulation regressions

Minimum Qualifications:
• Scripting in Python, Tcl, or Perl
• Git, Perforce, env module, shell setup/scripting
• Verilog and SystemVerilog and UVM
• Incisive/VCS, vManager, JasperGold, Design Compiler, IXCOM, Verdi, SimVision
• Continuous Integration Tools (Jenkins)
• Extensive debug of complex automation workflows
• Programming skills in C and C++

Preferred Qualifications:
• BS or MS degree in Electrical Engineering or equivalent; 5 years of practical experience
• A good understanding of the complete verification life cycle (test plan, testbench through coverage closure)
• Extensive knowledge of verification EDA tools
• Extensive knowledge in multiple testbench structures
• Proficiency in UVM
• Knowledge of assertion-based formal verification
• Knowledge of CPU and SOC microarchitectures
• Knowledge of FPGA and emulation platforms
• Solid understanding of industry standard tools for Sim, Formal, Lint, FPGA and Emulation platforms
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