Position Title: Senior IC Layout Designer
Location: San Diego, CA
Full-time: Salary + Benefits
• 5+ years of experience
• Hands-on experience with FinFET CMOS technologies (≤ 10nm).
• Experience with the layout of high performance custom digital standard-cells.
• Experience with full library characterization and deployment.
• Experience with Cadence, Mentor and Synopsys suite of design tools (Virtuoso Schematic and Layout, Calibre, etc.).
• Good understanding of engineering principles, such as matching, shielding, high-speed layout techniques.
• Ability to work in close collaboration with the designers to achieve a fully optimized layout and with other layout engineers for seamless integration in a digital flow.
• Good knowledge of device reliability mechanisms, electromigration, latch-up, guard-rings, DNW, IO-Ring building, STI, ESD, parasitics optimization and advanced process effects such as LOD and LDE.
• Experience with scripting languages such as: Skill, Perl, Python, etc.
• Self-motivated and creative candidate open to learn new skills and being able to work in a dynamic start-up environment.
• Experience in TSMC 7/6nm and/or Samsung 5/4nm.
• Experience with Asynchronous cells such as (Mueller cells, mutex, etc.).
• Experience with digital top-level integration (ICC, Innovus, etc.).
• Experience with managing layout resources to meet schedules and ensuring accountability.