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Senior Design Verification Engineer

Longmont, CO
Position Title: Design Verification Engineer
Location: 100% remote
Full-time: Salary + Benefits + Bonuses

About the Project:
As a senior member of an SOC development team, you would be responsible for driving the Design Verification of either blocks (units) or full-chip elements of innovative ASIC designs or blocks.  You will leverage your Functional Verification experience to develop Verification plans, create environments and tests to stress the correctness and effectiveness of features with an emphasis on multi-CPU implementation.  If you have SOC Verification experience building SystemVerilog/UVM-based environments and stimulus, directing random testing and deploying a coverage-based approach, joining the Encore Semi Verification team could be for you.

Minimum Qualifications:
• Functional Design Verification of logic blocks within an ASIC or SoCs including creation of the testplan and verification infrastructure, writing tests and driving functional coverage and debugging failures
• Strong experience with SV for Verification as well as experience with UVM
• Strong debugging experience
• Knowledge of other languages used in Verification which could include C/C++ tests or scripting languages such as Python
• BSEE with 7+ years of experience as a Verification Engineer
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