Position Title: Senior FPGA Verification Engineer
Work Location: 100% remote
Full-time: Salary + Benefits + Bonuses
Immediate need for one team Lead and one mid-to-senior Engineer. The program has 3 FPGA designs that are written VHDL and they are seeking to perform risk reduction. The team will need to determine whether we will use a VHDL verification testbench or SV/UVM. The preference if starting from scratch would be to use SV/UVM. In this case, we have from now until the end of the year to get as far as we can – get as far as possible with creating a testbench for the 3 modules. The 3 modules have been around for a decade or more, so the VHDL is pretty well solidified. The testbenches will need to be checked to see if there is much to start from or if starting over is necessary.
• FPGA Design experience
• Experience with digital channelized receiver/radio domain