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Senior Synthesis Engineer (100% remote)

San Jose, CA
Job Title: Senior Synthesis Engineer
Work Location: 100% remote/work from home
Full-time: Salary + Benefits + Bonuses or Contractor (Corp-Corp/1099)
Work Status: US Citizen only

Responsibilities:
• Responsible for Verilog register-transfer (RTL) to gate-level netlist implementation of customer specific systems on a chip (SOCs)
• Synthesize RTL (using Synopsys DC-Compiler) to meet physical and timing requirements and verify logical equivalency
• Solve synthesis correlation issues with internal team and client
• Support the development of chip-level sign-off timing constraints
• Analyze timing results and find creative solutions to enable quick timing closure
• Implement engineering change orders (ECOs) to address functional bugs to ensure the successful closure of designs
• Contribute to the advancement of internal methodologies and improvements of our flows through proficiency in PERL and tool command language (TCL) scripting languages

Requirements:
• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 8+ years of related professional experience
• Master’s degree and/or PhD in Computer Science, Electrical Engineering, or related fields with 5+ years of experience
• Must be a US Citizen
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