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Senior/Staff SerDes Circuit Design Engineer

Santa Clara, CA
Job Title: Senior/Staff SerDes Circuit Design Engineer
Location: Hybrid Onsite/Remote
Full-time: Salary + Benefits + Bonuses or Contractor
Work Status: US Citizen or US Permanent Resident

We are building a SerDes team for a new customer project. You will own (based on experience) TX, RX, COMMON or AMS block circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, clock generation and distribution, etc.). You will be working with multi-functional teams to define requirements/specs (e.g., modeling, package, board, DFT, ESD, etc.), crafting block-level specifications based on link-budget, behavioral modeling, and transistor-level feasibility. You will also drive mask design to implement layout view of designs. We also are working on Generation/QA of various IP Kit views/files for release to IP consumers, defining production/bench-level test-plans, and conducting design reviews of blocks with peers/management to show design meets spec targets and requirements.

Key Qualifications:
• The ideal candidate should have deep understanding of analog mixed-signal design with experience in high-speed serial links.
• Solid understanding and experience of designing analog mixed signal circuit blocks including Bandgap, biasing circuits, high-speed amplifiers, comparators, ADCs, DACs, Oscillators, Filters, PLL, DLL.
• In-depth knowledge of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques
• Experience with Tx/Rx analog and digital equalization techniques and circuits like de-emphasis, CTLE, DFE, FFE
• Experience with high-speed digital circuits (e.g., serializer, de-serializer, phase interpolator, etc.)
• Familiarity with CDR architectures and implementations 
• Required experience in advanced FinFET CMOS technology (10nm and below)
• Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, characterization, and bench evaluation
• Experience in lab testing of high-speed serial links
• Knowledge of common high-speed SerDes protocols (e.g., USB, SATA, PCIe, DDR, etc.)

Desired Experience:
• USB type C standard
• Modeling of digitally assisted analog adaptive loops (using C, MATLAB, Simulink, Python, etc.)
• Able to build VerilogA/AMS behavioral models
• Able to analyze and lead characterization data from lab and volume testing
• Knowledge of ESD requirements 
• Static timing analysis tools (e.g., Primetime, Tempus, etc.)

Education & Experience:
• BSEE with 7+ years, MSEE with 5+ years or PhD with 3+ years of proven experience.
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