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Senior Static Timing Analysis (STA) Engineer

Austin, TX
Job Title: Static Timing Analysis (STA) Engineer
Location: 100% remote / work from home
Full-time: Salary + Benefits + Bonuses or Contractor
Work Status: US Citizen or US Permanent Resident

As a member of the Encore Semi Physical Design team, you will perform various types of timing closure tasks, run and analyze STA. You will also work with the rest of the team members to modify timing constraints, run LEC and generate UPF files. As a Timing Engineer, you will work with RTL designers, block level and top-level physical designers to run, analyze timing, and drive timing closure of complex SoC devices in 16 nm FinFET technology.

• BSEE required with 7+ years of experience
• MSEE preferred with 5+ years of experience
• Experience in STA and timing closure of high-performance SOC designs in sub-micron technologies using Cadence Tempus
• Knowledge of all aspects of timing including noise, cross-talk and others
• Knowledge of basic SoC architecture and Verilog HDL
• Experience in timing flows with industry standard tools
• Experience in all aspects of timing closure for multi-clock domain designs
• Experience in deep submicron process technology nodes is strongly preferred
• Experience with STA on large SOC with multiple timing corners
• Experience with Timing ECO implementation
• Familiar with circuit modeling, transistor fundamentals and worst-case corner selection 
• Solid understanding industry standard tools for synthesis, place & route and tape-out flows
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