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Senior Design Verification (sub-system level) Engineer

Los Angeles, CA
Position: Senior Design Verification (sub-system level) Engineer
Work Location: 100% remote / work from home
Full-time: Salary + Benefits + Bonuses or Contractor
Work Status: US Citizen, US Permanent Resident or TN visa
Duration: 12-24 months, with multiple client-projects to follow

Job Description:
As Senior Design Verification Engineer, you will work on improving the verification methodology and test coverage. You will be responsible for developing test plans, testbenches, drivers, monitors and checkers/scoreboard, testcases, coverage analysis and simulation, verify the functionality, performance and other aspects of RTL designs mostly at the block-level. You will work very closely with the Architecture, RTL/uArch, cross-functional teams, and chip-level verification engineers.

Minimum Qualifications:
• BS/MS in Computer Science/EE with 8+ years of experience
• Experience with block level, cluster level or chip/SoC level verification including experience with high-speed interfaces and protocols
• Proficiency in UVM methodology, Constrained Random, Coverage Driven Methodology, Verilog, SystemVerilog
• Expertise in scripting languages, Python or Perl

Preferred Qualifications:
• Knowledge of MIPI or other relevant high-speed interfaces and protocol
• C/C++ experience
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