Position: Senior Design Verification (chip-level) Engineer
Work Location: 100% remote / work from home
Full-time: Salary + Benefits + Bonuses or Contractor
As Senior Design Verification Engineer, you will work on improving the verification methodology and test coverage for complex SoC devices. You will be responsible for developing test plans, testbenches, and perform simulations to verify the interconnect, functionality, performance and other aspects of RTL designs at the chip-level. You will work very closely with the Architecture, RTL/uArch, cross-functional teams, and block-level verification engineers. Responsibilities also includes DFT (scan, JTAG, BIST).
• BS/MS in Computer Science/EE with 8+ years of experience
• Experience with cluster level or chip/SoC level verification including experience with high-speed interfaces and protocols
• Experience with top-level verification using C
• Proficiency in UVM methodology, Constrained Random, Coverage Driven Methodology, Verilog, SystemVerilog
• Expertise in scripting languages, Python or Perl
• Strong debug skills and experience with debug tools such as Verdi
• Proficiency in industry DFT tools
• C/C++ experience
About Encore Semi
is a successful SoC Design and Software Engineering Services company headquartered in San Diego, California. We build Centers of Expertise (CoEs), engineering teams onsite or 100% remote, to support our many customers in North America. Our teams of experts contribute to leading-edge projects in the areas of SoC design and embedded software. We provide high-value through acceleration, performance improvement, optimization, and risk mitigation.
Encore Semi provides its engineering team members with continuous exposure to top advanced technologies and tools, participation in challenging yet exciting projects, and direct collaboration with its industry-leading teams, customers, and long-term partners.
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