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Sr Formal Verification Engineer
Irvine, CAJob Title: Senior Formal Verification Engineer
Full-time: W2 Hourly + Benefits + Bonuses or Contractor
Work Status: US Citizen / US Permanent Resident
Location: Remote in US only
As a Formal Verification Engineer assigned to our customer's RISC-V project, you will be responsible for ensuring the correctness of processor designs. In this role you will be involved in creating innovative solutions to verify complex designs in the form of micro-architecture and RTL. You will collaborate closely with design teams to enhance micro-architecture and contribute to the development of reusable verification models.
Responsibilities:
Work on verification of RISC-V processor designs
Work on creative solutions for verifying complex design micro-architectures
Generate comprehensive Formal Verification test plans
Execute Formal Verification flow and report design bugs, and work closely with design teams to help improve the micro-architecture
Develop re-usable verification models
Background requirements:
MSEE, BSEE or MSCS, BSCS, or equivalent
8+ years of verification experience, with at least 2 years utilizing formal verification methods
Solid understanding of RTL design and computer architecture
Proficiency in scripting languages Python, Ruby, or Perl
Preferred knowledge of SystemVerilog and UVM
Familiarity with low-power implementation (UPF)
The anticipated annual base salary for this position is between $145,000 to $175,000 which also includes a comprehensive benefits package.
Full-Time Benefits:
• 15 days of PTO per calendar year
• 10 paid Holidays per calendar year
• Comprehensive Medical Benefits: Company pays 80% of medical premium for Employee and Dependents
• Dental & Vision: Company pays 50% of Dental and Vision premiums for Employee and Dependents
• Voluntary Benefits: Dental & Vision Insurance, FSA, HSA and Gap Insurance
• Employee Assistant Program (EAP)
• 401k Traditional & Roth
• Life/AD&D and Long-Term Disability
• Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
Our management team is dedicated to this policy with respect to recruitment, hiring, placement, promotion, transfer, training, compensation, benefits, employee activities, and general treatment during employment.
Full-time: W2 Hourly + Benefits + Bonuses or Contractor
Work Status: US Citizen / US Permanent Resident
Location: Remote in US only
As a Formal Verification Engineer assigned to our customer's RISC-V project, you will be responsible for ensuring the correctness of processor designs. In this role you will be involved in creating innovative solutions to verify complex designs in the form of micro-architecture and RTL. You will collaborate closely with design teams to enhance micro-architecture and contribute to the development of reusable verification models.
Responsibilities:
Work on verification of RISC-V processor designs
Work on creative solutions for verifying complex design micro-architectures
Generate comprehensive Formal Verification test plans
Execute Formal Verification flow and report design bugs, and work closely with design teams to help improve the micro-architecture
Develop re-usable verification models
Background requirements:
MSEE, BSEE or MSCS, BSCS, or equivalent
8+ years of verification experience, with at least 2 years utilizing formal verification methods
Solid understanding of RTL design and computer architecture
Proficiency in scripting languages Python, Ruby, or Perl
Preferred knowledge of SystemVerilog and UVM
Familiarity with low-power implementation (UPF)
The anticipated annual base salary for this position is between $145,000 to $175,000 which also includes a comprehensive benefits package.
Full-Time Benefits:
• 15 days of PTO per calendar year
• 10 paid Holidays per calendar year
• Comprehensive Medical Benefits: Company pays 80% of medical premium for Employee and Dependents
• Dental & Vision: Company pays 50% of Dental and Vision premiums for Employee and Dependents
• Voluntary Benefits: Dental & Vision Insurance, FSA, HSA and Gap Insurance
• Employee Assistant Program (EAP)
• 401k Traditional & Roth
• Life/AD&D and Long-Term Disability
• Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
Our management team is dedicated to this policy with respect to recruitment, hiring, placement, promotion, transfer, training, compensation, benefits, employee activities, and general treatment during employment.