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Sr ASIC Design Engineer
San Jose, CAJob Title: SeniorASIC Design Engineer
Full-time / Contract
Work Status: US Citizen / US Permanent Resident
Location: Onsite
Encore Semi is seeking an exceptional ASIC RTL Design Engineer with a focus on Synthesis and Timing to join our innovative team. The candidate will be responsible for constraint generation and timing analysis of our next-generation AI chips. In this position you will work with microarchitecture, RTL design, and top-level physical design teams to run, analyze timing and drive timing closure of complex SoC devices. The design is a state-of-the art ASIC device implemented in 4 nm FinFET technology.
Responsibilities:
Understand the SOC architecture at RTL level
Write constraints and synthesis scripts
Execute STA timing runs at block level and SoC top level
Analyze timing and work with DFT teams to facilitate logic changes required
Drive timing analysis and closure of chips at block, cluster, and full chip level
Work with CAD team to implement timing infrastructure
Document and help with timing methodology definition
Work with DFT engineers with timing closure for various modes, such as scan and BIST
Minimum Qualifications:
Experience in STA and timing closure of high-performance SOC designs in sub-micron technologies
Knowledge of basic SoC architecture and Verilog HDL coding
BS degree in Electrical Engineering with 7+ years of practical experience
Preferred Qualifications:
Experience in timing flows with industry standard tools
Hands-on experience with synthesis and timing tools (Genus, Tempus, Design Compiler, Primetime, Timing Constraints Manager, Fishtail)
Experience in deep submicron process technology nodes is strongly preferred (4 nm or 5 nm)
Experience with STA on large SOC with multiple timing corners
Experience with Timing ECO implementation
Background in domain-specific STA and timing convergence, particularly with GPUs, CPUs
Experience in methodology and/or flow development, as well as automation
MSEE with 10 years of practical experience
The anticipated annual base salary for this position is between $160,000 to $190,000, which also includes a comprehensive benefits package.
Full-Time Benefits:
• 15 days of PTO per calendar year
• 10 paid Holidays per calendar year
• Comprehensive Medical Benefits: Company pays 80% of medical premium for Employee and Dependents
• Dental & Vision: Company pays 50% of Dental and Vision premiums for Employee and Dependents
• Voluntary Benefits: Dental & Vision Insurance, FSA, HSA and Gap Insurance
• Employee Assistant Program (EAP)
• 401k Traditional & Roth
• Life/AD&D and Long-Term Disability
• Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
Our management team is dedicated to this policy with respect to recruitment, hiring, placement, promotion, transfer, training, compensation, benefits, employee activities, and general treatment during employment.
Full-time / Contract
Work Status: US Citizen / US Permanent Resident
Location: Onsite
Encore Semi is seeking an exceptional ASIC RTL Design Engineer with a focus on Synthesis and Timing to join our innovative team. The candidate will be responsible for constraint generation and timing analysis of our next-generation AI chips. In this position you will work with microarchitecture, RTL design, and top-level physical design teams to run, analyze timing and drive timing closure of complex SoC devices. The design is a state-of-the art ASIC device implemented in 4 nm FinFET technology.
Responsibilities:
Understand the SOC architecture at RTL level
Write constraints and synthesis scripts
Execute STA timing runs at block level and SoC top level
Analyze timing and work with DFT teams to facilitate logic changes required
Drive timing analysis and closure of chips at block, cluster, and full chip level
Work with CAD team to implement timing infrastructure
Document and help with timing methodology definition
Work with DFT engineers with timing closure for various modes, such as scan and BIST
Minimum Qualifications:
Experience in STA and timing closure of high-performance SOC designs in sub-micron technologies
Knowledge of basic SoC architecture and Verilog HDL coding
BS degree in Electrical Engineering with 7+ years of practical experience
Preferred Qualifications:
Experience in timing flows with industry standard tools
Hands-on experience with synthesis and timing tools (Genus, Tempus, Design Compiler, Primetime, Timing Constraints Manager, Fishtail)
Experience in deep submicron process technology nodes is strongly preferred (4 nm or 5 nm)
Experience with STA on large SOC with multiple timing corners
Experience with Timing ECO implementation
Background in domain-specific STA and timing convergence, particularly with GPUs, CPUs
Experience in methodology and/or flow development, as well as automation
MSEE with 10 years of practical experience
The anticipated annual base salary for this position is between $160,000 to $190,000, which also includes a comprehensive benefits package.
Full-Time Benefits:
• 15 days of PTO per calendar year
• 10 paid Holidays per calendar year
• Comprehensive Medical Benefits: Company pays 80% of medical premium for Employee and Dependents
• Dental & Vision: Company pays 50% of Dental and Vision premiums for Employee and Dependents
• Voluntary Benefits: Dental & Vision Insurance, FSA, HSA and Gap Insurance
• Employee Assistant Program (EAP)
• 401k Traditional & Roth
• Life/AD&D and Long-Term Disability
• Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
Our management team is dedicated to this policy with respect to recruitment, hiring, placement, promotion, transfer, training, compensation, benefits, employee activities, and general treatment during employment.