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Sr Low Power Design Engineer
San Jose, CAJob Title: Sr Low Power Design Engineer
Full-time + Benefits + Bonuses
Work Status: US Citizen / US Permanent Resident
Location: San Jose CA
Job Description:
We are seeking a Low Power Design Engineer with expertise in Unified Power Format (UPF), low power design methodologies, and architecture development. The ideal candidate will work closely with cross-functional teams to optimize power consumption at various stages of the design process, from RTL to synthesis and P&R.
Key Responsibilities:
Define and implement UPF-based power intent for low-power ASIC/SoC designs.
Develop low power design strategies at both RTL and physical design levels, including clock gating, power gating, multi-Vt optimization, and DVFS techniques.
Collaborate with RTL designers and synthesis teams to ensure power-efficient architecture and implementation.
Work on low power synthesis and P&R flows, optimizing power, performance, and area (PPA).
Utilize EDA tools for power analysis, optimization, and verification across the design flow.
Contribute to architectural decisions impacting power, performance, and efficiency.
Required Skills & Qualifications:
Strong experience with UPF-based power intent development and verification.
Proficiency in low power design techniques at RTL, synthesis, and P&R levels.
Work on low power synthesis and P&R flows, optimizing power, performance, and area (PPA) using Innovus and Fusion Compiler
Knowledge of EDA tools for power estimation and optimization (e.g., PrimePower, PTPX, PowerArtist, Joules, Voltus, or similar).
Experience in RTL design (Verilog/SystemVerilog) and synthesis (DC, Genus, or similar).
Understanding of physical design constraints related to power optimization.
Familiarity with power analysis methodologies and simulation tools.
Preferred Qualifications:
Experience with advanced process nodes (7nm, 5nm, 3nm, etc.).
Hands-on experience in dynamic/leakage power analysis and reduction.
Exposure to formal verification of low-power design intent.
The anticipated annual base salary for this position is between $155,000 to $175,000, which also includes a comprehensive benefits package.
Full-Time Benefits:
• 15 days of PTO per calendar year
• 10 paid Holidays per calendar year
• Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
• Dental & Vision: Company covers 50% of premiums for Employee and Dependents
• Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
• Employee Assistant Program (EAP)
• 401k - Traditional & Roth
• Life/AD&D and Long-Term Disability
• Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
Our management team is dedicated to this policy with respect to recruitment, hiring, placement, promotion, transfer, training, compensation, benefits, employee activities, and general treatment during employment.
Full-time + Benefits + Bonuses
Work Status: US Citizen / US Permanent Resident
Location: San Jose CA
Job Description:
We are seeking a Low Power Design Engineer with expertise in Unified Power Format (UPF), low power design methodologies, and architecture development. The ideal candidate will work closely with cross-functional teams to optimize power consumption at various stages of the design process, from RTL to synthesis and P&R.
Key Responsibilities:
Define and implement UPF-based power intent for low-power ASIC/SoC designs.
Develop low power design strategies at both RTL and physical design levels, including clock gating, power gating, multi-Vt optimization, and DVFS techniques.
Collaborate with RTL designers and synthesis teams to ensure power-efficient architecture and implementation.
Work on low power synthesis and P&R flows, optimizing power, performance, and area (PPA).
Utilize EDA tools for power analysis, optimization, and verification across the design flow.
Contribute to architectural decisions impacting power, performance, and efficiency.
Required Skills & Qualifications:
Strong experience with UPF-based power intent development and verification.
Proficiency in low power design techniques at RTL, synthesis, and P&R levels.
Work on low power synthesis and P&R flows, optimizing power, performance, and area (PPA) using Innovus and Fusion Compiler
Knowledge of EDA tools for power estimation and optimization (e.g., PrimePower, PTPX, PowerArtist, Joules, Voltus, or similar).
Experience in RTL design (Verilog/SystemVerilog) and synthesis (DC, Genus, or similar).
Understanding of physical design constraints related to power optimization.
Familiarity with power analysis methodologies and simulation tools.
Preferred Qualifications:
Experience with advanced process nodes (7nm, 5nm, 3nm, etc.).
Hands-on experience in dynamic/leakage power analysis and reduction.
Exposure to formal verification of low-power design intent.
The anticipated annual base salary for this position is between $155,000 to $175,000, which also includes a comprehensive benefits package.
Full-Time Benefits:
• 15 days of PTO per calendar year
• 10 paid Holidays per calendar year
• Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
• Dental & Vision: Company covers 50% of premiums for Employee and Dependents
• Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
• Employee Assistant Program (EAP)
• 401k - Traditional & Roth
• Life/AD&D and Long-Term Disability
• Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
Our management team is dedicated to this policy with respect to recruitment, hiring, placement, promotion, transfer, training, compensation, benefits, employee activities, and general treatment during employment.