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Sr Design Verification Engineer (Remote)
Chandler, AZSr Design Verification Engineer
Location: Remote (Anywhere in USA)
Full-time: Salary + Benefits + Bonuses / Contractor
Work Status: US Citizen
We’re looking for a Senior Digital Design Engineer to lead the development of advanced ASIC/SoC architecture. In this role, you’ll define specs, build complex RTL designs (Verilog/SystemVerilog), drive verification (UVM/TLM), and guide projects from concept to silicon. You’ll collaborate across teams, support synthesis, timing, DFT, and test, and help mentor junior engineers.
Skills:
Full-Time Benefits:
• 15 days of PTO per calendar year
• 10 paid Holidays per calendar year
• Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
• Dental & Vision: Company covers 50% of premiums for Employee and Dependents
• Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
• Employee Assistant Program (EAP)
• 401k - Traditional & Roth
• Life/AD&D and Long-Term Disability
• Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
Location: Remote (Anywhere in USA)
Full-time: Salary + Benefits + Bonuses / Contractor
Work Status: US Citizen
We’re looking for a Senior Digital Design Engineer to lead the development of advanced ASIC/SoC architecture. In this role, you’ll define specs, build complex RTL designs (Verilog/SystemVerilog), drive verification (UVM/TLM), and guide projects from concept to silicon. You’ll collaborate across teams, support synthesis, timing, DFT, and test, and help mentor junior engineers.
Skills:
- Bachelor’s/Master’s in EE/CS or similar
- Min 10+ years of ASIC/SoC design experience
- Strong RTL design and verification background
- Proficiency with Synopsys/Mentor EDA tools and scripting (Python, TCL, etc.)
- Leadership mindset and a track record of first-pass silicon success
Full-Time Benefits:
• 15 days of PTO per calendar year
• 10 paid Holidays per calendar year
• Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
• Dental & Vision: Company covers 50% of premiums for Employee and Dependents
• Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
• Employee Assistant Program (EAP)
• 401k - Traditional & Roth
• Life/AD&D and Long-Term Disability
• Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.