Physical Design Engineer (ASIC/SoC) - Onsite Clearance Requirement: Active Secret Clearance (or ability to obtain and maintain one) About the Role Are you ready to design the future of aerospace and defense technology? We are looking for a talented and highly motivated Physical Design Engineer to join our Advanced Microelectronics team. In this role, you will play a critical part in the development of next-generation ASICs and SoCs that power mission-critical systems. Own the physical implementation of complex, high-performance, and low-power designs from netlist through GDSII tape-out. Working alongside a collaborative team of digital design, verification, and systems engineers, you will leverage industry-leading EDA tools to ensure our silicon meets the rigorous performance, power, and area (PPA) targets required for national security applications. Key Responsibilities Netlist-to-GDSII Execution: Drive block-level and chip-level physical implementation, including floorplanning, power grid design, placement, clock tree synthesis (CTS), and routing using Synopsys Fusion Compiler. Timing Closure: Perform rigorous Static Timing Analysis (STA), constraint validation, and timing closure using Synopsys PrimeTime across multiple corners and operating modes. Power & Reliability Analysis: Conduct dynamic and static IR-drop analysis, as well as Electromigration (EM) checks, using Ansys Redhawk to ensure robust power delivery and design reliability. Physical Verification: Execute and debug Design Rule Checks (DRC) and Layout Versus Schematic (LVS) checks to ensure manufacturing compliance and flawless tape-outs. Methodology Improvement: Collaborate with cross-functional teams to refine physical design methodologies, automate repetitive workflows using Tcl/Python, and optimize the overall PPA. Required Qualifications Clearance: Must be a U.S. Citizen with an Active U.S. Secret Clearance (or the ability to obtain and maintain one). Education: Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field. Experience: Proven industry experience in ASIC/SoC physical design and tape-out cycles. Tool Proficiency:  Hands-on expertise with Fusion Compiler (or equivalent place-and-route tools like IC Compiler II/Innovus). Deep knowledge of STA and sign-off timing closure using PrimeTime. Experience with EM/IR analysis using Redhawk. Proficiency in physical verification (DRC/LVS) sign-off tools (e.g., Calibre, IC Validator). Scripting: Strong scripting skills in Tcl, Python, or Perl to automate EDA flows. Problem Solving: Exceptional analytical skills and the ability to debug complex layout, timing, or integration issues autonomously. The anticipated annual base salary for this position is between $170,000 to $210,000, which also includes a comprehensive benefits package. Full-Time Benefits: • 15 days of PTO per calendar year • 10 paid Holidays per calendar year • Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents • Dental & Vision: Company covers 50% of premiums for Employee and Dependents • Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance • Employee Assistant Program (EAP) • 401k - Traditional & Roth • Life/AD&D and Long-Term Disability • Tuition reimbursement Equal Opportunity Policy Statement Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances. Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.