Senior Analog Layout Designer

Location: San Diego, CA, United States
Date Posted: 12-10-2018
Position Title: SerDes IP Layout Designer
Locations: San Diego, CA or Bay Area, CA
Status: Full-time

About the Team:

In support of the high-demand from our customers, the Physical Design Group is expanding and recruiting new members in the area of High-Speed SerDes Layout. The focus of this team is to implement complex, high speed analog and some high-speed custom digital circuits for High-Speed Serial IO interfaces for SoC and ASIC applications. We partner with the top-tier SoC companies to implement designs from RTL to tapeout, on today’s most complex process technologies, using the latest EDA tools and physical implementation methodologies.

About the Project:

As a member of the growing Next Generation Process Design and Layout team, the ideal candidate will have extensive experience with the layout of analog and high-speed custom analog/digital circuits for High Speed Serial IO Interface IPs to be used in SoC applications.  Applicants must have several years of experience in this area and experience using the design tools associated with these tasks, preferably Cadence tools, as well as familiarity with current CMOS technology generations (22nm and below). Potential candidate has capacity to learning new tools, methodologies, and technology. Applicants must be good team players. Knowledge and/or experience with Serial Link applications is a significant plus.

Minimum Qualifications:

• 6+ years of custom layout design experience with a focus on analog and mixed signal designs
• Deep Experience with layout in the Cadence Design Environment 
• Familiarity with Virtuoso XL 
• Experience must include floorplanning 
• Experience includes collateral generation (GDS, LEF), and able to run checking such as LVS & DRC, ERC, RV, etc.
• Experienced with Electromigration and voltage drop analysis 
• Ability to recognize critical signal nets and reduce parasitics by proper floorplanning/placement 
• Excellent communication skills and ability to work within a tightly-coupled team are a must

Preferred Qualifications:

• Work experience with FinFET-based technologies (Intel 22/14/10nm, TSMC 16FF, Samsung 14FF, or below) is highly preferred     
• Experience with Cadence Innovus or Synopsys ICC tools and flows is a plus 
• EE with an emphasis in analog circuit design is preferred

Education Requirements:

• Bachelor's, Electrical Engineering + 6 years experience
• Associate’s, Electrical Engineering + 12 years experience
 
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