Senior DFT Engineer

Location: San Jose, CA, United States
Date Posted: 12-10-2018
Position Title: Senior DFT Engineer
Location: Bay Area, CA
Status: Full-time

About the Team:
In support of the high-demand from our customers, the Physical Design Group is expanding and recruiting new members in the area of implementation of SoCs and complex IP. The focus of this team is to implement complex, high speed analog and high-speed digital circuits for High-Speed Serial IO interfaces suited for SoC and ASIC applications. We partner with the top-tier SoC companies to implement designs from RTL to tape-out, on today’s most complex process technologies, using the latest EDA tools and physical implementation methodologies.

About the Project:
As a member of the growing Next Generation Process Design and Layout team, the ideal candidate will have extensive experience with Design for Test (DFT) methodologies. You will be responsible for executing DFT tasks such as generating RTL for test functions, integrating DFT logic for IP blocks, scan insertion, ATPG, MBIST and JTAG. You will work with analog and digital design teams on DFT architecture/partitioning/implementation for complex IP and SoC devices. Applicants must have extensive experience in this area and proven ability using the design tools associated with these tasks, preferably Synopsys tools, as well as familiarity with logic design, static timing analysis (STA), simulation, and formal verification.

Minimum Qualifications:
• At least 7 years of experience with industry standard DFT tools
• RTL design proficiency, ability to integrate DFT with existing design
• Experience with, scan insertion, MBIST and JTAG
• Ability to work independently and being the DFT owner for the design
• Experience supporting ATPG and test generation
• Ability to run Logic Equivalency Checks
• ATPG pattern verification with gate level simulations
• Testbench generation and functional simulations and test vector preparation
• Good communications skills
• Scripting proficiency with Perl, TCL or other scripting language

Preferred Qualifications:
• Work experience with Synopsys DFT tools TetraMAX/DFTMAX/DFT Compiler
• Experience with synthesis and STA

Education Requirements:
• Bachelor's, Electrical Engineering + 7 years’ experience
• MSEE preferred


About Encore Semi:

Encore Semi is a successful Engineering Solutions company. We build Centers of Expertise to support our many customers from the semiconductor and electronics system industry in North America. Our teams of experts contribute to leading-edge projects in the areas of SoC design and embedded software. We provide high-value through acceleration, performance improvement, optimization, and risk mitigation.

Encore Semi provides its engineering team members with continuous exposure to top advanced technologies & tools, participation in challenging yet exciting projects, and direct collaboration with its industry-leading teams, customers, and long-term partners. Learn more about the company’s great benefits and career path on our website.
#EncoreSemiCareers
this job portal is powered by CATS