Position Title: Senior Design Verification Engineer
Location: El Segundo, CA
Status: Full-time (salary + benefits + bonuses)
About the Team:
Join the growing Encore Semi Front-End Development team to collaborate with customers to design, verify and enable various subsystems and full-chip for current and next generation ASICs and SOCs. Building on your background of SV/UVM-based Design Verification, you would join a team integrating internal and 3rd party IPs into SOCs and verifying overall functional correctness.
About the Project:
As a senior member of an ASIC development team, you will be responsible for building a Functional Verification environment for new designs incorporating internally developed and 3rd party IPs. You will leverage your SV/UVM experience verify interfaces and focus testing on corner cases in the full-chip such as interrupt and exception protocols as well as overall data and control flow. If you have SOC Integration Verification experience implementing SV/UVM environments and stimulus, directing random stimulus and deploying a coverage-based approach, joining the Encore Semi Verification team could be for you.
• Functional (Design) Verification at the SOC or “Full-Chip” level using simulation models. Experience should include creating Verification Plans from the Microarchitecture Specifications and ability to understand the RTL
• SV/UVM methodology expertise to create Verification environments and drive Functional Verification including the incorporation of internal IPs and 3rd party IPs from different suppliers
• Experience stressing full-chip protocols and flushing out bugs at the full-chip level
• Experience debugging RTL simulations including waveform-based debugging.
• 7+ years of Design Verification experience including working with RTL Developers
• Verification experience focused in any of the following areas of ASIC/SOC designs:
- Processor cores (including ARM cores)
- Interfaces such as PCIe Gen 3 or 4, RapidIO, Ethernet switching
- General control logic
• Experience developing Verification methodologies or environments incorporating various levels of coverage but, most importantly, functional coverage (as opposed to code or statement coverage).
• Required: Bachelor's, Electrical Engineering
• Preferred: Master's, Electrical Engineering