Position Title: Senior DFT Engineer (must have an active DoD Security Clearance)
Location: Remote/work from home + some travel to Linthicum Heights, MD (near Baltimore)
Status: Full-time (salary + benefits + bonuses)
About the Team:
In support of the high-demand from our customers, the Physical Design Group is expanding and recruiting new members in the area of implementation of SoCs and complex IP. The focus of this team is to implement complex, high speed analog and high-speed digital circuits for SoC and ASIC applications. We partner with the top-tier SoC companies to implement designs from RTL to tape-out, on today’s most complex process technologies, using the latest EDA tools and physical implementation methodologies.
About the Project:
As a member of the Design implementation team, the ideal candidate will have extensive experience with Design for Test (DFT) methodologies. You will be responsible for executing DFT tasks such as generating RTL for test functions, integrating DFT logic for IP blocks, scan insertion, ATPG, MBIST and JTAG. You will work with analog and digital design teams on DFT architecture and implementation for complex IP and SoC devices. Applicants must have extensive experience in this area and proven ability using the design tools associated with these tasks, as well as familiarity with logic design, static timing analysis (STA), simulation, and formal verification.
• Due to the nature of the projects and facilities where you will be working, US Citizen and an active DoD Clearance is a requirement.
• 6+ years of experience implementing DFT for large ASIC devices
• Experience with industry standard DFT tools, preferably Mentor Graphics Tessent
• Experience with, hierarchical scan insertion, MBIST and repair and 1149.6 BS
• Experience with test bring-up and debug
• Experience supporting ATPG test generation and test compression
• Good understanding of timing concepts and STA experience
• Scripting proficiency with Perl, TCL or other scripting languages
• RTL coding experience in Verilog / VHDL for ASICs or FPGAs
• Experience designing with either internal interfaces (such as ARM interconnects like AXI or proprietary interconnects) or external interfaces (such as PCIe, networking, SRIO, etc)
• Experience with IJTAG IEEE 1687 and IEEE 1500 is a plus
• Required: Bachelor's, Electrical Engineering
• Preferred: Master's, Electrical Engineering