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Senior PCIe Design Verification Engineer

San Diego, CA
Position Title: Senior PCIe Design Verification Engineer
Location: San Diego or remote/work from home
Full-time: Salary + Benefits + Bonuses

About the Project:
As a senior member of an SOC development team, you will be responsible for the Functional Verification of the 3rd party PCIe PHY IP with the PCIe controller using SV/UVM environments with the goal of quickly finding bugs in the design. You would be responsible for verifying the various protocols including clocking, reset, and DFT for the subsystem as well as the overall functionality of the PCIe protocols. If you have experience with Functional Verification of SOCs or Units with a heavy control logic focus using SV/UVM, directed random stimulus and a coverage-based methodology, joining the Encore Semi Verification team could be for you.

Minimum Qualifications:
• Experience with Functional (Design) Verification at the SOC or “Full-Chip” level 
• Experience with PCIe Physical Layer (PHYs) and PCIe controllers – especially the transport layers  
• Strong expertise with SV/UVM methodology to create Verification environments and drive Functional Verification
• Experience debugging in an RTL simulation environment including waveform-based debugging.
• 7+ years of Design Verification experience including working with RTL Developers

Preferred Qualifications:
• Experience with SOC design verification at the Full Chip or IP Level
• Verification experience on complex SOCs / ASICs with multiple embedded processors 
• Experience developing Verification methodologies or environments incorporating various levels of coverage but, most importantly, functional coverage (as opposed to code or statement coverage).

Education Requirements:
• Required: Bachelor of Science, Electrical Engineering (BSEE)
• Preferred: Master of Science, Electrical Engineering (MSEE)
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