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Senior DFT Engineer

San Diego, CA
Job Title: Senior DFT Engineer
Location: San Diego, CA or Remote (work from any US location)
Status: US Citizen or US Permanent Resident only

You will be responsible for DFT (Design-for-Test) aspects of ASIC Design. You will have a thorough understanding of digital design concepts and have prior experience with ASIC development process. Must be knowledgeable in VHDL, Verilog or SystemVerilog RTL coding and be highly proficient in DFT methodologies. You will have an ability to operate in a team environment and collaborate across the different teams as required to accomplish the goals.

• Experience with Siemens Tessent and/or Cadence Modus is a must
• BSEE required with 7+ years of pure-DFT engineering experience
• At-speed scan testing
• Cadence, Mentor and/or Synopsys test insertion and ATPG tools
• Generating test patterns and analyzing and debugging test failures
• Hierarchical scan testing, IEEE-1500 and/or IEEE-1687, and test compression
• Integrating DFT features of 3rd party IP
• Proficiency in HDL (VHDL/Verilog/SystemVerilog)
• JTAG IEEE-1149.1 and IEEE-1149.6 (AC JTAG)
• Knowledge of Synthesis, P&R and Static Timing Analysis would be a plus
• Memory BIST and logic BIST
• Proficiency in scripting languages such as Tcl, Python or Perl
• Working with test engineers to implement ATPG vectors on tester hardware

The anticipated annual base salary for this position is between $130,000 - $180,000 which also includes a comprehensive benefits package.


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