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SoC and NoC Cache Coherency Architect

San Jose, CA
Job Title: SoC and NoC Coherency Architect
Location: San Jose, CA
Status: US Citizen or US Permanent Resident only

Responsibilities:
Cache Coherency Architecture:
• Evaluate existing, industry standard, cache coherency protocols, maintain and improve our proprietary coherency protocol which is used within company's highly configurable NoC IP
• Develop comprehensive and scalable cache coherency architectures that align with the overall System-on-a-Chip (SoC) design
• Analyze our customer's requirements for cache coherent system architectures, also considering partitioning large designs into chiplets using die-to-die and chip-to-chip architectures based on industry wide standards like CXL, UCIe and PCIe
• Set performance goals (PPA) for the configurable IP

NoC Integration:
• Collaborate with SoC design teams to ensure seamless integration of cache coherency into the SoC architecture
• Help to optimize Cache Coherency Architecture and uArchitecture within the NoC to minimize latency and improve BW

Performance and Power Optimization:
• Analyze performance bottlenecks and power consumption aspects, proposing and implementing innovative solutions to enhance overall efficiency
• Collaborate with hardware and software teams to verify and optimize cache coherency mechanisms

Protocol Verification:
• Support the verification team to develop verification strategies to ensure the correctness and robustness of the cache coherency protocols and the implementation within our NoC IP
• Support the emulation teams testing and debugging to validate cache coherency behaviors under various scenarios for functional correctness and performance

Cross-Functional Collaboration:
• Interact with the marketing and sales teams to collect customer input and understand market and product requirements
• Collaborate with hardware design, software development, and system architecture teams to understand their needs and issues
• Provide technical expertise and support to the FAE team to assist in the integration of our products within our customer's designs

Industry Research and Innovation:
• Stay up-to-date with the latest advancements and research in cache coherency and NoC technologies.
• Evaluate emerging methodologies, standards, and industry trends, proposing their integration to enhance our NoC IP offerings.

Documentation and Communication:
• Prepare detailed technical documentation, including architecture specifications and design guidelines/white papers.
• Effectively communicate complex technical concepts to both technical and non-technical stakeholders.

Qualifications:
• BS/MS degree in Electrical Engineering, Computer Engineering, or a related field.
• Proven experience as a Cache Coherency Architect, Design Engineer, or similar role with a focus on NoC IP development.
• In-depth knowledge of SoC and NoC architecture, cache coherency protocols, and memory hierarchy.
• Strong understanding of cache hierarchies and their interaction with NoC interconnects.
• Experience in cache coherency verification and validation techniques.
• Familiarity with hardware description languages (HDLs) and SoC design tools.
• Strong analytical and problem-solving skills with a strategic mindset.
• Excellent communication and collaboration abilities to work effectively with diverse teams and stakeholders.
• Familiarity with hardware description languages (HDLs) and design tools used in NoC IP development or prior experience in designing coherent systems is highly advantageous.


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The anticipated annual base salary for this position is between $175,000 to $235,000 which also includes a comprehensive benefits package.

 

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